Logic Synthesis for Programmable Devices Onur Bay & Debatosh Debnath

Problem Statement For large functions, two-level networks are difficult to generate and manipulate. In order to efficiently implement logic functions in many programmable devices two-level networks should be converted into networks with three or more levels. Among three-level networks OR-AND-OR and AND-OR- EXOR networks are proven to be powerful architectures. Large two-level networks first need to be partitioned into small sub-networks and then converted into three-level networks. To address these problems a computer-aided design (CAD) tool is under development to optimally partition large networks into manageable sub-networks and then synthesize optimized OR-AND-OR and AND-OR-EXOR networks.

Design Flow Our project aims to address Logic Synthesis part of the design flow.

FPGAs FPGAs (Field-Programmable Gate Arrays) are used to implement digital circuits. Gate array allows reprogramming. Applications of FPGAs include DSP, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, and a growing range of other areas.

CPLDs CPLDs (Complex Programmable Logic Devices) are also reprogrammable. The building blocks of a CPLD is macrocells which contain logic to implement sum-of- products (SOP) expressions and specialized logic operations.

CPLD Macrocells Able to implement OR-AND-OR or AND-OR-EXOR three level networks

Three-level OR-AND-OR network OR-AND-OR networks have almost sufficient number of levels to implement many logic functions. They have lower and more predictable delay. They prevent exponential growth of two-level networks for implementing many logic functions. AND-OR OR-AND-OR

Three-level AND-OR-EXOR network It is one of the efficient three level architecture. Often prevents exponential growth of two-level networks. In many cases it requires fewer gates than OR- AND-OR architecture. Has predictable delay. C out AND-OR-EXOR network AND-OR AND-OR-EXOR

Partitioning Multi-Level Networks Partitioning is a technique to divide a network into a collection of smaller sub-networks. Synthesis tools often cannot cope with the complexity of the entire system under development. The present state of design technology often requires a partitioning of the system. As the target architecture is fixed in most applications, their types and their geometric arrangement are given, the partitioning task is to find a mapping of the system’s objects to the FPGAs while satisfying constraints. Partitioning divides a network into sub-networks while minimizing the number or weight of the edges cut by the operation.

Our Approach Design methods for three-level networks require two- level networks. Large multi-level networks are difficult to convert into two-level forms. We partition a given multi-level network into smaller multi-level sub-networks. The sub-networks are then converted into two-level networks which are then represented as optimized OR- AND-OR and AND-OR-EXOR networks. These three-level networks are then implemented into CPLDs.

References 1.Altera Corporation, MAX 7000A Programmable Logic Device Family Data Sheet, Oct S. Brown and J. Rose, FPGA and CPLD architectures: A tutorial, IEEE Design & Test of Computers, Vol. 13, No. 2, pp , Summer D. Debnath and Z. G. Vranesic, A fast algorithm for OR-AND-OR synthesis, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 22, No. 9, pp , Sept A. Jabir and J. Saul, Minimization algorithm for three-level mixed AND-OR-EXOR/AND-OR-EXNOR representation of Boolean functions, IEEE Proceedings---Computers and Digital Techniques, Vol. 149, No. 3, pp , May C. Alpert and A. Kahng, Recent directions in netlist partitioning: A survey, Integration: the VLSI Journal, Vol. 19, pp , 1995.