Encryption Transaction with 3DES Team W2 Yervant Dermenjian (W21) Taewan Kim (W22) Evan Mengstab(W23) Xiaochun Zhu(W24) Objective: To implement a secure credit card transaction using 3DES encryption and Kerberos-style authentication. Current Stage: Architecture Proposal 01/26/2004 Design Manager: Rebecca Miller

 Identity theft is a growing problem  Sensitive information never transmitted  Uses existing cards and phone network  Credit and charge card fraud costs cardholders and issuers hundreds of millions of dollars each year Security In Making Purchases

Encryption/Decryption Example  Input : Credit Information  Output : Cipher Text Credit #: Credit #: Security code: 319 Security code: 319 Input Pin # : 4510 Input Pin # : 4510 key1: 0x32, 0x37, 0x33, 0x39, 0x38, 0x32, 0x30, 0x31 key1: 0x32, 0x37, 0x33, 0x39, 0x38, 0x32, 0x30, 0x31 key2: 0x34, 0x38, 0x35, 0x36, 0x32, 0x33, 0x38, 0x39 key2: 0x34, 0x38, 0x35, 0x36, 0x32, 0x33, 0x38, 0x39 key3: 0x33, 0x31, 0x39, 0x34, 0x35, 0x31, 0x30, 0xFF key3: 0x33, 0x31, 0x39, 0x34, 0x35, 0x31, 0x30, 0xFF Expiration Date: 08/2008 Expiration Date: 08/2008 Plain Text : 0x30, 0x38, 0x2F, 0x32, 0x30, 0x30, 0x38, 0xFF Plain Text : 0x30, 0x38, 0x2F, 0x32, 0x30, 0x30, 0x38, 0xFF 0x2F, 0x81, 0xA8, 0xBF, 0x3C, 0x6B, 0xDF, 0xB4 0x2F, 0x81, 0xA8, 0xBF, 0x3C, 0x6B, 0xDF, 0xB4

3DES Algorithm Flowchart (I) DES DES -1 DES Plain Text DES -1 DES Cipher Text K1K1K1K1 K2K2K2K2 K3K3K3K3 Encryption Decryption

3DES Algorithm Flowchart (II) 64 bit plain Text cipher Text Initial Permutation Final Permutation 16 Rounds Encryption Extension 32 bit 48 bit 48 Bit XOR S Box 32 Bit XOR Right Half Left Half Subkey SingleRound

3DES Algorithm Flowchart (III) Final Permutation 48 bit Sub-key [ I ] I=16? Key Schedule 56bit Key I=1 Left/Right Half 28 bits Left Barrel Shift Initial Permutation I=I+1 Ready Y N

Verification of 3DES in C

I/O Pins  Required Inputs:  Provided Output : 32 bits data input at pins 32 bits data input at pins 1 bit reset at pin 1 bit reset at pin 1 bit encryption/decryption mode control at pin 1 bit encryption/decryption mode control at pin 32 bits data output at pins 32 bits data output at pins 1 bit ready at pin 1 bit ready at pin 1 bit clock at pin 1 bit clock at pin

Block Diagram Key2 56’b SRAM Barrel Shifter I: 0,0,1,1,1,1,1,1,0,1,1,1,1,1,1,0 PC-2 (wiring) Key set Current and next keys 2 x 48’b Register 48’b 32’b 56’b 1’b 56’b 48’b PC (wiring) XOR Expansion 32’b 48’b Plaintext 64’b SRAM R[I] 32’b L[I] 32’b S-box 8x4x16x4’b ROM L[I-1] 32’b R[I-1] 32’b XOR 48’b 64’b Register P 32’b Key1,3 56’b SRAM 32’b output 32’b input demux 16’b ROM IP -1 (wiring) 32’b input 64’b mux 32’b mux

S Box 4LUT 16x4bit ROM 4LUT 16x4bit ROM 4LUT 16x4bit ROM 4LUT 16x4bit ROM Mux FF 4 {1:6} {2:5} {1},{6} {6} {1} 4 4

Architecture Analysis  The Key schedules can be pinelined with the encryption process. While the key[I-1] is used to encrypt the text, the key[I] will be generated at the same time.  SRAM is used to store the keys and the plain text; 2x48’b registers are used to store the sub-keys during scheduling  Permutation is implemented by wiring  The data input pins are designed to be 32 bits. We need to clock over 2 clock cycles for 64 bits keys; 32 output pins need to clock over 2 clock cycles for the 64 bits cypher text.

Behavior Verilog Test Bench

Transistor Estimation (I)  Transistor Count for Key Schedule 2 x 56 bits SRAM: 672 T 2 x 56 bits SRAM: 672 T 2 x 28 bits Barrel Shifter: 112 T 2 x 28 bits Barrel Shifter: 112 T 160 X 2-1 Mux/Demux:645 T 160 X 2-1 Mux/Demux: 645 T 2 x 48 bits Register: 2 x 48 bits Register: 1152 T PC (4 bit Adder & 4bit Register): PC (4 bit Adder & 4bit Register): 160 T lookup table(16 bit ROM&4bit Decoder): lookup table(16 bit ROM&4bit Decoder): 104 T Control Logic: Control Logic: 500 T

Transistor Estimation (II)  Transistor Count for Encryption Process 1 x 64 bits SRAM: 384 T 1 x 64 bits SRAM: 384 T 80 bit XOR: 640 T 80 bit XOR: 640 T 8 x S Box (256bits ROM & 6 bit Decoder) : 5728 T 2 x 64 bits Register: 2 x 64 bits Register: 1536 T PC (4 bit Adder & 4bit Register): PC (4 bit Adder & 4bit Register): 160 T 192 x 2-1 Mux/Demux: 192 x 2-1 Mux/Demux: 1536 T Control Logic: Control Logic: 500 T  Total Transistor Count:  Total Transistor Count: ~ T

Current Status  Design Proposal (100% done)  Architecture Proposal (100% done) High Level Simulation by C code High Level Simulation by C code Mapping of algorithm into hardware Mapping of algorithm into hardware Behavioral Verilog simulation and test bench Behavioral Verilog simulation and test bench  To be done Floor Plan Floor Plan Gate-level design Gate-level design Chip Layout Chip Layout

Design Decisions  Store only 2 keys at a time  Reduce Barrel shifting control values from 1/2 to 0/1 to use only a single bit  Two memory blocks for keys used so Key1 does not have to be inputted twice for Key3

Problems and Questions  Should we choose SRAM or registers to store the sub-keys after scheduling?  Permutation implemented by wiring may cause messy wire crossover. Can we implement this with logic?  The transistors required to store all sub-keys is very large. We hope to be able to only store two sub-keys at a time.