Uli Schäfer 1 JEM1: Status and plans JEM1.1 Status Plans

Uli Schäfer 2 Largely identical to JEM 1.0 Additional daughter module: Control Module (CM) CAN VME control Fan-out of configuration lines JEM1.1

Uli Schäfer 3 JEM status 4 JEM 1.0 main boards available 3 are fully working, 1 has short on TTCdec module connector 1 JEM 1.1 main board available, so far ok. All populated with input modules 5 new G-link modules available Assembled by Bruno So far 3 working 0-version of control module No CAN No VME CPLD Sum processor configuring from flash (ACE, working now!), all others via VME  JEM1s working (standard tests) Firmware (sum, input) stable - new readout format successfully tested

Uli Schäfer 4 JEM1 status : tests JEM tests done in Mainz, at RAL and CERN test beam Up to 4 JEMs in a 9U crate allowing for FIO tests either direction, along with VMM, TCM, CMM (and CPMs!) External data sources for LVDS : 1 DSS 16-channel (MZ) Several DSS (RAL) LSM (RAL) PPr (RAL, CERN - 4 channels) External data sinks for Merger signals : 2 CMMs (RAL) Readout path: Complete ROS (RAL, CERN) G-link tester with f/w pattern comparison (MZ)

Uli Schäfer 5 JEM1.0 status : tests System tests at RAL: (from June 2004) DSS  JEM  crate CMM  system CMM  ROD  ROS  ROD  ROS Comparing readout data against simulation. Data taken up to 5 slices of JEM DAQ data. Trigger rate up to 60kHz, 4*10 6 events analysed, no errors observed on JEM readout. Interface tests: LVDS inputs, merger outputs, FIO, readout links BER measured, no errors in (CMM,FIO), (ROD), bits (LVDS)

Uli Schäfer 6 FIO tests : delay scan All data latched into jet processor on a common clock edge Sweep TTCrx delay setting, 104ps steps Measure data errors on each channel : 10 bits, 5 signal lines Single channel 8ns error free All channels 6.5ns error free  All interfaces ok, timing ok, latency within budget (<9.5 ticks) But: noise observed on FIO lines…

Uli Schäfer 7 JEM1 noise problem FIOs using 1.5V DCI/60Ω signalling. CMOS thresholds 35%/65% Noise observed close to thresholds (full activity) Screen shot typical, not worst case: All signal lines active -- 1 input proc. -- every other off

Uli Schäfer 8 JEM1 problems Difficult to distinguish cross talk ground bounce FPGA pins / vias, daughter module GND connection Check on merger lines: 2.5V signals Noise 1.25 V pp

Uli Schäfer 9 JEM1 noise Current assumption: Noise might have several contributions but dominated by crosstalk: buses are typically 30cm long, 130µ tracks, 290µ pitch  160µ gap No effort available for simulation  Build test board with widely spaced 60Ω tracks (.46 mm)

Uli Schäfer 10 Various track densities Varied GND return quality (GND shields) No results yet Cross-talk tester

Uli Schäfer 11 JEM1.2  Design JEM1.2 with wide spacing (~.5mm?)  Need more routing space, signal layers,… Significant amount of design work

Uli Schäfer 12 JEM1.2 Signal layers: 2 microstrip 2 striplines 1 dual-stripline Micro-vias Blind vias.4mm Buried vias Total: 2.2mm Components on bottom!

Uli Schäfer 13 Plans Continue cross-talk tests Layout JEM with widened data buses Further design work required JTAG test adapters Input modules (add voltage/temperature sensor) Control module (add CAN / VME / configuration circuitry) Readout tests (9U RODs) Further tests with stress patterns required on all interfaces, particularly on FIOs Tests at elevated temperature ? Further LVDS tests required (LSM, PPR) PRR in August ? Production time ~8 weeks Need test rig in MZ (or HD?) LSM / GIO / CMM ? / ??? !!!! Lead time for FPGAs !!!!