1. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 1 The First Integration Test of the ATLAS End-cap Muon Level 1 Trigger System Introduction Overview of ATLAS End-cap Muon Level1 Trigger TGC electronics (Level1 Trigger + TGC Readout) Slice Test Setup Test Results Summary Chikara Fukunaga Tokyo Metropolitan University On behalf of the ATLAS TGC electronics group

2. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 2 Introduction 3 main ASICs out of total 7 have been made with full specifications. Stand-alone tests of ASICs have been finished. An overall integrated test has been required with all these ASICs in one test bed →Slice test (SLT) system. C++ based trigger simulation program has been needed and developed, and it could give the test patterns and answers to the SLT system. Integration test started in Sept.,’01, all the components have been installed in Aug.,’02.

3. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 3 Overview of ATLAS End-cap Muon Level1 Trigger M1 M2 M3 Thin Gap Chamber (TGC) 1.05    2.70, z = ±14m r (wire)-  (strip) readout Total 150 K channels for Trigger Total 7 layers (M1,M2 and M3) Low-pT Trigger, p T ≥ 6 GeV M1(3) triplet: 2 out of 1, 1out of 2 M2(2) vs. M3(2) doublets: 3 out of 4 Hi-pT Trigger, p T ≥ 20 GeV M1 vs. doublets (M2&M3) Sector Logic (SL) R-  coincidence, Highest p T tracks To Muon Central Trigger Proc. I/F

4. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 4 TGC electronics (Level1 Trigger + TGC Readout) M3 M2 M1 On detector part Off detector part

5. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 5 Slice Test (SLT) Setup

6. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 6 SLT Components I– PS Board & ASICs SLB ASIC 0.35  m 250K gates Low-pT Trigger Readout buffer PP ASIC 0.6 → 0.35  m 50K gates Analog+digital LVDSrx Fine delay Bunch Crossing ID Trigger (Hi-pT) Readout (SSW)

7. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 7 SLT Components II - Hi-pT board & ASIC LVDS in From PS board G-link out To SL Hi-pT ASIC 0.35mm 80Kgates Hi-pT trigger Hitachi BGA

8. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 8 SLT Components III – Readout System LVDS in From PS board (SLB) G-link out To ROD Star Switch (SSW) Read Out Driver (ROD) G-link in From SSW FIFO SDRAM CPU

9. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 9 SLT Components IV – Software system Integrated control software based on the ATLAS online SW framework SLT requires initialization and module/ASIC configuration at beginning Run control for run start/stop Run Control GUI & Status Window Configuration DataBase Editor Window

10. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 10 SLT Results I – Trigger Part Logic Verification of Trigger Logic (Simulation vs. HW) The same trigger hit patterns used for the simulation were inputted to PPG (pulse Pattern generators), and compared outputs of the SLT system with one of the simulation: Generated Trigger Hit patterns, and comparison with the simulation 1 track (~20000) → No error found. 2 tracks (~20000) → No error found. ≥ 3 tracks (~15000) → No error found.

11. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 11 SLT Results II - Trigger Latency Stage SLT Measurement Required upper limit TGC, ASD160175 PP ASIC4350 SLB ASIC4975 LVDS Tx,Rx8375 Cable 15m75 Hi-pT ASIC5575 G-link Tx,Rx10575 Cable (90m)450 SL160175 Cable (5m)25 Total12051250 Latency Measurement = Actual Measurement (PS board, HiPT and SL) AND Cable length Estimation 1205ns (SLT) < 1250ns (RUL)

12. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 12 SLT Results III – Readout test Since SSW has been delivered in this summer, full test of PS-board→SSW→ROD has not been done. PS-board→PT4(SSW alternative)→ROD has been checked in 2001 with long run tests. 400 clock counts (40MHz) can be used for SLB or SSW readout if Level 1 rate is 100KHz. SLB uses 218 counts. If TGC occupancy is 4%, SSW needs 160 counts. SSW will not be bottle neck. (TGC Occupancy ~ 1%)

13. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 13 SLT Results - ROD ROD (Read Out Buffer) has several problems. 4 bytes access to internal bus takes 0.2  s. SSW No hits = 4bytes SSW Hits = 40bytes If all 13 SSWs have no hits, 14  s, if all hits, 30  s. One ROD with 13 SSWs can be done with 30~70KHz (< 100KHz). We need design modification. ROD Structure

14. 14/November/2002 CF NSS2002 in Norfolk, Virginia, USA 14 Summary BlockTestStatus Trigger Part Integration@40MHz Done, pattern check OK Latency OK 1205  s<1250  s Readout Part IntegrationNot yet, stand-alone Readout Rate SSWOK 100KHz Readout Rate ROD30~70KHz Software Online DAQ OK, will be used for beam Trigger Logic Simulation Need improvements Control System HSC-CCIOK for config. ASIC