1 کلاس جبراني  پنجشنبه 26 فروردين: ساعت 8:00 صبح ميان ترم  سه شنبه 3 ارديبهشت: ساعت 9:30 صبح.

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PLDs ROM : Programmable OR array

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Presentation transcript:

1 کلاس جبراني  پنجشنبه 26 فروردين: ساعت 8:00 صبح ميان ترم  سه شنبه 3 ارديبهشت: ساعت 9:30 صبح

Programmable Logic PAL, PLA

3 Integration SSI  Small-Scale Integration −Several gates in a package MSI  Medium-Scale Integration −Tens of gates in a package LSI  Large-Scale Integration −Hundreds to hundred thousands of gates in a package VLSI  Very Large-Scale Integration −More than above −E.g. Microprocessors.

4 SSI (7400 Series)

5 DIP Dual in-line Packages

6 PLAs Programmable Logic Array  Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making/ breaking connections among the gates.  General purpose logic building blocks.

7 PLA

8

9 A 3×2 PLA with 4 product terms.

10 Design for PLA: Example  Implement the following functions using PLA F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Personality Matrix 1 = asserted in term 0 = negated in term - = does not participate Input Side: 1 = term connected to output 0 = no connection to output Output Side: OutputsInputsProduct term Reuse of terms A B C F F F F A B B C A C B C A

11 Example: Continued F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Personality Matrix

12 Constants  Sometimes a PLA output must be programmed to be a constant 1 or a constant 0. −P1 is always 1 because its product line is connected to no inputs and is therefore always pulled HIGH; −this constant-1 term drives the O1 output.  No product term drives the O2 output, which is therefore always 0.  Another method of obtaining a constant-0 output is shown for O3.

13 BCD to Gray Code Converter W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' Minimized Functions:

14 4 product terms per each OR gate A B C D A BD BC W X Y Z BC’ B C BCD AD’ BCD’ Product terms cannot be shared ! PLA achieves higher flexibility at the cost of lower speed!

15 PALs Programmable Array Logic  a fixed OR array.

16 PAL inputs 1 st output section 2 nd output section 3 rd output section 4 th output section Only functions with at most four products can be implemented

17 PAL W = ABC + CD X = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD x x x

18

19 Tri-State (Output Enable) Gate Tri-State (Three-State) Inverter:  The output in NOT of input if the Enable input is HIGH  Else Hi-Impedance (Hi-Z) −Unconnected. Enable input output input Enable Tri-State (Three-State) Buffer:

20 Active Low Input Tri-State Buffer with Active Low Enable: Tri-State Inverter with Active Low Enable: in out EN in out EN 3-state BUF, EN low 3-state INV, EN low

21 Helper Terms  If an I/O pin’s output- control gate produces a constant 1,  the output is always enabled, but the pin may still be used as an input too.  outputs can be used to generate first- pass “helper terms” for logic functions that cannot be performed in a single pass with the limited number of AND terms available for a single output.