הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Virtex II-PRO Dynamical Test Application Performed By: Luba Khaskin Raziel Einhorn Instructor: Ina Rivkin Spring 2004

Table of contents ● Background - Space Compatibility ● Project Goals ● Virtex II-Pro Overview ● Block Diagram ● Project guidelines ● Design tools ● Schedule

Virtex II-Pro Evaluation Board (platform) DUT Host JTAG PortSerial Port Outputs (Leds, LCD)Input (DIP Switches, Push Buttons) Test Environment VHDL DesignerXilinx Tools GUIHyper Terminal

Background-Space Compatibility ●In space, electronic modules are exposed to great amount of radiation. ●The outcome is both temporary damage – like bit changes, and permanent damage – physical destruction of the device. ●As for today, space-compatible devices are being manufactured in a separated procedure, which is more expensive and complicated than the one being used for non-space (civilian) devices. ●As always, the goal is to reduce satellites’ costs. Therefore, one of the ways will be examining possible space-compatibility of civilian devices, in order to integrate them in the satellites.

●One of the system modules being examined is the Xilinx Virtex II-Pro. ● In previous project, the V2P was examined statically: testing the device’s functionality before and after radiating it. ●In this project, following the previous one, we will examine ways to test its functionality dynamically: under real-time radiation conditions similar to those in space. ●We will concentrate in examining the device’s robustness to temporary damage and it’s ability to recover in a case of an error.

Project Goals ●Our desire is to maximize the tests’ mapping of each component while checking its functionality by evaluating the statistical number of errors occurred. ●The final product will be a hardware application which will run the tests and read the outputs. ●We would also like to create a user-friendly GUI (Graphical User Interface), which will supervise the test procedure and display the results in a way which will enable easy processing. ●Since the final product of the previous project was also hardware application with GUI, our ambition is to create an add-on to the existing GUI, which will supervise both static and dynamic test procedures.

The Virtex II-Pro – Components Configurable logic blocks (CLB) 18Kb Block-RAMs 44 18X18 bit multipliers Gbps Rocket I/O transceivers 4 Digital Clock Manager units (DCM) Power-PC 405 CPU

Virtex II-Pro Overview - Platform Input: Push buttons, Dip Switches Output: User Led, LCD Input/Output: JTAG Port,System Ace, Parallel Cable, Cpu Trace Port Cpu Debug Port,Rocket I/O RS232 Port,Clock Generator P160 Module

Project guidelines ●Memory and memory-like components (BRAM, CPU internal memory, LUT…) will be tested by loading and reading back data, then verifying its intactness. ●Various test procedures for other components (Rocket I/O, DCM, Configuration area…) will be developed and examined during the project.

Design Tools ●HDL Designer (VHDL) – creating hardware applications ●ModelSim – VHDL simulation ●Simplifier – synthesis tool ●Xilinx ISE – Place & Route ●EDK – PPC implementation ●Visual Basic – designing the GUI

Schedule – First Semester ●Learning VHDL design tools and other development tools ●Getting familiar with the V2P and its development environment ●Determine the test algorithms ●Creating the test vectors for each component

General Schedule In the first semester, we will concentrate on the internal components of the device, developing and improving test algorithms. In the second semester, we will approach the processor (using EDK), and will test it using the knowledge we have acquired during the first part of the project.