Sept 25, 2008 PHENIX RPC review C.Y. Chi 1 RPC Front End Electronics On chamber discriminator  The strips  The CMS discriminator chips  The discriminator.

Slides:



Advertisements
Similar presentations
RPC Electronics Overall system diagram Current status At detector
Advertisements

JLab High Resolution TDC Hall D Electronics Review (7/03) - Ed Jastrzembski.
The MAD chip: 4 channel preamplifier + discriminator.
S. Veneziano, Lecce 21 February 2002 RPC readout and trigger electronics status Lecce 21/02/2002.
SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.
The EMMA Turn-by-Turn BPM System A. Kalinin ASTeC Daresbury Laboratory STFC EMMA Commissioning Workshop Daresbury Laboratory, 21 May 2009.
1 (Gerard Visser – US Belle II Electronics Meeting 7/15/2011) Belle-II bKLM Readout System Concepts, &c. W. Jacobs, G. Visser, A. Vossen Indiana University.
Status of the LHCb RPC detector Changes with respect to Note cm strips instead of 3 cm (cost optimization) All gaps same size (standardization)
RPC Electronics Status Overall system TDC –Digitizing frequency issue (determine the bin size of the TDC value) Discriminator test result Trigger module.
July 10, 2008 PHENIX RPC review C.Y. Chi 1 RPC Front End Electronics On chamber discriminator  The strips  The CMS discriminator chips  The discriminator.
RPC Electronics Overall system diagram –At detector –Inside racks Current status –Discriminator board –TDC board –Remaining task.
August SGSS front end, Summary August 2008 Edwin Spencer, SCIPP1 SGST Preview SCIPP, UC Santa Cruz Andrey Martchovsky Gregory Horn Edwin Spencer.
Mauro Raggi Status report on the new charged hodoscope for P326 Mauro Raggi for the HODO working group Perugia – Firenze 07/09/2005.
Status of LAV FEE electronics G. Corradi, C. Paglia, D. Tagnani & M. Raggi, T. Spadaro, P. Valente.
U niversity of S cience and T echnology of C hina Design for Distributed Scheme of WCDA Readout Electronics CAO Zhe University of Science and Technology.
Preliminary Design of Calorimeter Electronics Shudi Gu June 2002.
Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.
MR (7/7/05) T2K electronics Beam structure ~ 8 (9?) bunches / spill bunch width ~ 60 nsec bunch separation ~ 600 nsec spill duration ~ 5  sec Time between.
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
A. Sukhanov, BNL1 NCC Electronics Readout of pad structured sensors ● High dynamic range: 14 bit range, 10 bit accuracy ● Summing signals from 6 detectors.
PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout.
M. Lo Vetere 1,2, S. Minutoli 1, E. Robutti 1 1 I.N.F.N Genova, via Dodecaneso, GENOVA (Italy); 2 University of GENOVA (Italy) The TOTEM T1.
September 8-14, th Workshop on Electronics for LHC1 Channel Control ASIC for the CMS Hadron Calorimeter Front End Readout Module Ray Yarema, Alan.
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
Update on the HBD Craig Woody BNL DC Meeting June 8, 2005.
HBD FEM Overall block diagram Individual building blocks Outlook ¼ detector build.
Updated HBD FEM Diagram Clock Master Clock fanoutADC Optical out Backplane Crate GTM/Ethernet New Daughter card + DCM Test pulse.
ASIC R&D at Fermilab R. Yarema October 30, Long Range Planning Committee2 ASICs are Critical to Most Detector Systems SVX4 – CDF & DO VLPC readout.
HBD FEE test result summary + production schedule 16mv test pulse result –5X attenuator + 20:1 resistor divider at input (to reduce the noise on the test.
NUMI Off Axis NUMI Off Axis Workshop Workshop Argonne Meeting Electronics for RPCs Gary Drake, Charlie Nelson Apr. 25, 2003 p. 1.
A. Ranieri / RPC-CMS Pre-loaded profile Synchronization & Control Board (SCB) The RPC electronics will consist of the FE board plus the Synchronization.
March 9, 2005 HBD CDR Review 1 HBD Electronics Preamp/cable driver on the detector. –Specification –Schematics –Test result Rest of the electronics chain.
Update on final LAV front-end M. Raggi, T. Spadaro, P. Valente & G. Corradi, C. Paglia, D. Tagnani.
1 07/10/07 Forward Vertex Detector Technical Design – Electronics DAQ Readout electronics split into two parts – Near the detector (ROC) – Compresses and.
HBD electronics status All the ADC and XMIT boards are installed. –Top 3 crates are for the ADC, XMIT boards –Bottom crate is for test pulse boards/future.
KLM Trigger Status Barrel KLM RPC Front-End Brandon Kunkler, Gerard Visser Belle II Trigger and Data Acquistion Workshop January 17, 2012.
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
HBD/TPC Electronics Status Works done to for a)Prototype detector readout b)Understand packing density and heat loading issues c)Address the overall system.
Fermilab Silicon Strip Readout Chip for BTEV
B.Satyanarayana Department of High Energy Physics Tata Institute of Fundamental Research Homi Bhabha Road, Colaba, Mumbai,
Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans.
TPC electronics Status, Plans, Needs Marcus Larwill April
Nov 1, 2007 IEEE NSS & MIC 2007 by C. Y. Chi 1 A Faster Digitizer System for the Hadron Blind Detector in the PHENIX Experiment Cheng-Yi Chi Nevis Lab.
HBD/TPC Electronics Status Works done to for a)Prototype detector readout b)Understand packing density and heat loading issues c)Address the overall system.
Plans to Test HBD Prototype in Run 6 Craig Woody BNL DC Meeting March 8, 2006.
PHENIX Safety Review Overview of the PHENIX Hadron Blind Detector Craig Woody BNL September 15, 2005.
1 Carleton/Montreal Electronics development J.-P Martin (Montreal) Shengli Liu & M. Dixit (Carleton) LC TPC Meeting DESY Hamburg, 4 June 2007.
MuTr Chamber properties K.Shoji Kyoto Univ.. Measurement of MuTr raw signal Use oscilloscope & LabView Read 1 strip HV 1850V Gas mixture Ar:CO 2 :CF 4.
Preparations to Install the HBD for Run 6 Craig Woody BNL PHENIX Weekly Meeting January 26, 2006.
VMM Update Front End ASIC for the ATLAS Muon Upgrade V. Polychronakos BNL RD51 - V. Polychronakos, BNL10/15/131.
CERN PH MIC group P. Jarron 07 November 06 GIGATRACKER Meeting Gigatracker Front end based on ultra fast NINO circuit P. Jarron, G. Anelli, F. Anghinolfi,
B => J/     Gerd J. Kunde PHENIX Silicon Endcap  Mini-strips (50um*2mm – 50um*11mm)  Will not use ALICE chip  Instead custom design based on.
Calorimeter Digitizer Electronics Cheng-Yi Chi Columbia University Nov 9-10, 2015sPHENIX Cost and Schedule Review1.
KLOE II Inner Tracker FEE
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
PSD Front-End-Electronics A.Ivashkin, V.Marin (INR, Moscow)
CMS EMU TRIGGER ELECTRONICS
Power pulsing of AFTER in magnetic field
Front-end electronic system for large area photomultipliers readout
Status of n-XYTER read-out chain at GSI
RPC Front End Electronics
BESIII EMC electronics
RPC Front End Electronics
RPC FEE The discriminator boards TDC boards Cost schedule.
RPC Electronics Overall system diagram Current status At detector
sPHENIX DOE-SC CD-1/3a Review WBS 1.5.3: CalElec Digitizers
Digitally subtracted pulse between
TOF & BB FEE Safety Review
PHENIX forward trigger review
Cheng-Yi Chi Nevis Lab Physics Dept Columbia University
Presentation transcript:

Sept 25, 2008 PHENIX RPC review C.Y. Chi 1 RPC Front End Electronics On chamber discriminator  The strips  The CMS discriminator chips  The discriminator board  Test results The TDC board  The TDC and Crate block diagram  The TDC board test result  The trigger board The board counts Status

Sept 25, 2008 PHENIX RPC review C.Y. Chi 2 RPC Strip Our chamber is closely follow the CMS design. Our on-chamber electronics will try to follow their electronics too. The CMS barrel strips is 1.3m long, 4 cm or 2cm wide.  15/40 ohms impedance. 420pf/160pf capacitance.  Fully terminated strips. CMS encap RPC  Cover 5/16 degree in phi, 7 to 38mm in width and 22 to 55 cm in length  Un-terminated.  Lemo cables are used to connect strip to the discriminator board PHENIX RPC strip width range from 11.4 mm by 141mm to 64.6 mm by 554.2mm.  The smallest one has 46 ohms impedance and 16 pf of capacitance.  The largest one has 10 ohms impedance and 286 pf of capacitance.

Sept 25, 2008 PHENIX RPC review C.Y. Chi 3 CMS RPC preamp/discriminator chip Build on AMS 0.8 um BiCMOS process, +5V device. 15 ohms input impendence. 45mW/channel. 8 channels per chip. It is designed in Bari, Italy. It has preamp, gain stage, zero crossing discriminator, monostable (cover the dead time) and LVDS driver. The chip is designed to deal with 20 fC up to 20 pC with1.7fC ENC noise. Zero crossing is necessary to deal with large dynamic range. The time walk is about.6ns except for very large charge. Testing show that threshold level could be as high as 100fc without loosing efficiency.

Sept 25, 2008 PHENIX RPC review C.Y. Chi 4 Chip production With help of Giuseppe Isaelli and Flavio Loddo from Bari Italy, we got 4 32 channel CMS boards about 1.5 years ago. These boards works both on the bench in Nevis and chamber testing in University of Colorado.  We decide to use the CMS RPC chip as the frontend discriminator chips. With help of Flavio, the chip production start at end of the last year.  The wafer is fabricated in AMS through EuroPratice and packaged in Taiwan  The chip testing is done by Matrix. (the same company did the CMS RPC chip testing)  The yield is around 99%, few bad chips out of ~2000 We now have twice more chips than we needed in hand.

Sept 25, 2008 PHENIX RPC review C.Y. Chi 5 Cable adapter board RPC 32 channel discriminator board 32 channels per board Fused +6V input analog/digital power supply ~.46A (use +5V, +3V through low drop regulators) Serial download is used to set 10 bits 4 channel threshold DAC (4mv per bin) and Fire test pulse. One DAC setting per chip. LVDS discriminator output Serial download The design is following closely the CMS design

Sept 25, 2008 PHENIX RPC review C.Y. Chi 6 RPC disc 32 ch 3M PL Or pl RPC TDC 64 ch Half octant Detector Module edge Adapter Board Adapter Board 2-3 m cable ?8-18 meters cable ? 2-3 m cable?8-18 meter cable ? 3M (Gray) M (Black) RB 3M (Gray) M N3432-L302RB 3M (Black) D89140-???? Signal Cable : 40 conductors twist flat ribbon cable 3M (gray) M M 1700/40 Twisted Pair, Flat Cable,.050" 28 AWG Stranded Fire rating VW-1 16 short RG174 cables Connection diagram

Sept 25, 2008 PHENIX RPC review C.Y. Chi 7 The discriminator’s threshold is moving 4mv per step. The test pulse is feed to the input amplify through 1pf cap. (not for calibration, functional check only) Channel 14 TDC distribution, DAC step =80 TDC step On board test pulse vs. threshold study TDC bin size ~2.5ns Range from 0 to 43

Sept 25, 2008 PHENIX RPC review C.Y. Chi 8 Direct Pulse Injection (fixed threshold) & Cross Talk Study Inject test pulse through the cable adapter card + 10pf capacitance (channel 45) 2mv per step, 160mv threshold (~80fc) Cross talk seen at round 100mv on channel 46. Input (steps) Channel 45 TDC Channel 46Channel 44 disc. fired No disc fired No disc fired

Sept 25, 2008 PHENIX RPC review C.Y. Chi 9 DISC LVDS output at discriminator board DISC output after ~10 meter cables 69 ns time difference 1.61ns/ft  ~42 ft Digitally subtracted pulse between + and – side of discriminator LVDS output 500mv per division 1.4V 1.63V Long output cable study 1

Sept 25, 2008 PHENIX RPC review C.Y. Chi 10 Short Cable Disc threshold TDCTDC 79 ft cable (~24 meters) Long output cable study mv/div 50ns/div The station 3 cable length could be along as 20 meters Although the result looks O.K., but this is in a lab environment. Digitally subtracted pulse

Sept 25, 2008 PHENIX RPC review C.Y. Chi 11 DISCDISC LVDS Receiver Trigger window 32 channel digitizer PLL Test Pulse LVDS Transmitter 4x beam clock 44X BC Test Pulse MASK Serial download Disc Serial download TDC serial download Interface Chip Collects 64 Channel Of Data Digitized Data L1 trigger etc L1 trigger primitives L1 trigger primitives Serial Download Timing etc. Event Data Event Data RPC TDC MODULE

Sept 25, 2008 PHENIX RPC review C.Y. Chi 12 The TDC Internal Test Pulse Scan test pulse step average TDC valueSigma on the TDC TDC: Use 44X beam crossing clock to digitized the discriminated LVDS pulse, ~2.5ns for 9.6MHz RHIC clock Test Pulse: Generated internally with the FPGA with the same 44x beam crossing clock Trigger Window: The lower and upper limits be can set channel by channel Mask: Mask bits can be set to turn off individual channel. Serial data to Discriminator Board: Control test pulse firing and discriminator threshold ( chip by chip) TDC Module

Sept 25, 2008 PHENIX RPC review C.Y. Chi 13 RPC(HBD) crate/BUS structure 6Ux160 mm VME size TDCTDC TDCTDC Output To L1 Clock fanout L1 primitives L1 GTM Slow Control TDCs XMIT DCM Clock Master RPC FEM crate optical cable

Sept 25, 2008 PHENIX RPC review C.Y. Chi 14 Trigger data from FEM 1 pair of cable per FEM Arria FPGA De-serialized FEM data & format trigger data Transceiver blocks RPC Trigger Board Optical transmitter 2.8 Gbits/sec RPC triggers has been layout and proceed to fabrication. The module can receive up to 6 (8) FEM’s trigger data The optical trigger data contains, idle, clock numbers and up to 12 16bits FEM trigger data every beam crossing.

15 Channel count etc… (one side) Station1a+b3total Channel Channel per FEM (TDC) 64 FEM (TDC)48 96 Disc Board L1 trigger Fibers 8816 FEM/ L1 fibers 66 Support board/crate 33 FEM/crate 12 Crates448 The discriminator board is mounted on chamber The TDC, Trigger module locate in the readout crate.

Sept 25, 2008 PHENIX RPC review C.Y. Chi 16 Production QA For discriminator boards  We do even/odd channel direct pulse inject through a 12 bits DAC pulser vs. threshold  We do on board test pulse test vs. threshold For TDC boards  Fire the discriminator on board test pulse can check the data  TDC internal test pulse scan  Data to L1 trigger board test. ( still need to be works out)

Sept 25, 2008 PHENIX RPC review C.Y. Chi 17 STATUS The discriminator and TDC modules has been successfully prototyped. Waiting for on chamber testing.  Grounding issue need to be resolved with chamber testing CMS 32 channel board has been tested in both Colorado and BNL factory. We are building, 40 discriminator modules, 20 TDC boards, 3 sets of crates+ clock master modules for the coming run and individual factory readout/test stand. Trigger modules is designed and proceed to fabrication.

Sept 25, 2008 PHENIX RPC review C.Y. Chi 18 Production Outlook The production cycle normally last about 6 months. This include, fabricate boards, buy parts, board assembly and testing.  For the RPC3 N discriminator board, we have most of parts on hand already. We will start production around Nov this year.