3D CMP and 3D IC Physical Design Flow Jason Cong and Guojie Luo University of California, Los Angeles {cong, cong,

2 Outline u Design Driver  3D Chip Multiprocessor Based on OpenRISC 1200 Based on OpenRISC 1200  NoC Interconnect  RF Reconfigurable Interconnects u Physical Design Flow  Design Flow for 3DM2  Design Flow in Development

3 3D Chip Multiprocessor (CMP) u Three Silicon Layers  Tier 3: Cache Data Components  Tier 2: Interconnect and Cache Tags  Tier 1: Cores u Non-Uniform Cache Access  Cores see different latencies to different cache banks  Data can migrate among distributed caches Can hide latency Can hide latency Adds interconnect traffic Adds interconnect traffic Heat sink

4 3DM2 - MITLL.18um 3D SOI Technology

5 3D CMP Test Chip Architecture u Using OpenRISC 1200   Open source in-order RISC uniprocessor  Has been tested in silicon and runs Linux  Simple core used due to test chip area constraints u MIT Lincoln Labs process  180nm, 25mm 2 x 3 tiers  Taped out on Nov 2006 L1 Inst L1 Data Priority Arbiter JTAG Debug Interface UART RS-232 L2 Cache Onchip RAM

6 3D CMP NoC Interconnect u One example NoC using two 5-port routers u Short vertical links to local L2 slices u Links to NoC fabric for remote L2 traffic Core L2 R R

7 3D Reconfigurable Interconnects u 3D Integration  Targets interconnect latency by reducing wirelength u RF Interconnects  Frequency-Division Multiple Access (FDMA)  Targets interconnect congestion by improving bandwidth Multiple signals can occupy a common interconnect Multiple signals can occupy a common interconnect  Further potential to dynamically tune frequencies Adapt to different communication patterns Adapt to different communication patterns Interconnect density can be reduced while minimizing performance impact Interconnect density can be reduced while minimizing performance impact Core A Bank 0 Core B Bank 1 Core C Bank 2 Core D Bank 3 AB 01 CD AB CD 0 A 1 B 2 C 3 D One shared RF Fabric can be configured to a wide range of topologies.

8 Carrier Frequency u On/off digital switching noise main source of noise couple to RF Interconnect u Higher freq carriers avoid all the base-band digital noise u Clock rate of future CPU not exceeding 4-5GHz (due to power consumption issues) u Bandwidth Base-band noise will be around the clock rate u We need to pick a freq far away from the noise u => f 1 = 8GHZ, f 2 = 16 GHz, f 3 = 24GHz, f 4 = 32GHz

9 Bi-Directional FDMA-Link/Bus Bi-directional Link Bi-directional Bus Advantages: Higher combined data rate Simultaneous, bi-directional communications Re-configurable between bands Low in-band coupling for parallel bus Potentially with fewer I/O pins and smaller routing area

10 FDMA-I I/O Data Eye Diagram

11 3D CMP Roadmap u 3D CMP with direct interconnects  Four OR1200 cores, four shared L2 cache banks, and a simple, static interconnect topology – implemented on an FPGA first and then fabricated at MIT LL u Simulation infrastructure to explore NUCA and RF design space  Dynamic adaptation of RF interconnect to a diverse set of multithreaded and multitasking applications u FPGA prototyping of core, bus structures, NUCA and RF  Choose the best power/performance point in the design space u Final implementation on a 3D process (MIT-LL)

12 Physical Design Flow for 3DM2 (1/2) Partition netlist Floorplan P/G network Place Trial Route (1)Place Macros (Memory) (2)Place Clock Via (3)Plan Signal Via Region RTL Synthesis RC extraction Clock Tree Route Routing Congestion Timing Constraint Layout Place P/G viaAlign Signal Via Match min/max Phase Delay on 3 tiers RC extraction DRC, LVS

13 Physical Design Flow for 3DM2 (2/2) u Most 3D features are handled manually u Ask for more 3D CAD tools

14 Thermal-Aware 3D Physical Design Flow Netlist (LEFDEF) Design constraints Technology CIF/GDSII ParasiticExtraction Thermal Simulation Simulation TimingAnalysis Thermal-Driven 3D Floorplanner 3D Floorplanner Thermal-Aware 3D Router w/ Thermal Via Planning OpenAccessOpenAccess Thermal-Driven 3D Placement CompactThermalmodelCompactThermalmodel LayoutVerification

15 R lateral Thermal Resistive Network [Wilkerson04] u u Circuit stack partitioned into tiles u u Tiles connected through thermal resistances   Lateral resistances: fixed   Vertical resistances  1/#via u u Heat sources modeled as current sources   Current value = power u u Heat sinks modeled as ground nodes (a) Tiles stack array (b) Single tile stack P1P1 R2R2 R3R3 R4R4 P4P4 P3P3 P2P2 R1R  R5R5 P5P5 5 Accurate and slow

16 Thermal-Aware 3D Floorplanning [ICCAD04] u Simulated Annealing (SA) Engine  New local z-neighbor operations  Cost function nwl  normalized wirelength nwl  normalized wirelength narea  normalized chip area narea  normalized chip area nvc  normalized interlayer via number nvc  normalized interlayer via number c T  temperature cost c T  temperature cost u Hybrid Thermal Evaluation  At each move ― uses simplified chain model  At each SA temperature drop ― the resistive network model

17 3D Placement via Transformation [ASPDAC 07] u Idea  Start from 2D placement  Heuristic 2D to 3D transformation Reduce long nets Reduce long nets Keep local connecting nets Keep local connecting nets  Window-based transformation balance WL and #via balance WL and #via  RCN graph based refinement Reduce #via and tempreture Reduce #via and tempreture

18 Multilevel TS-Via Planning and 3D Routing [ASPDAC’05 & ICCAD’05] u Alternating Direction TS-Via Planning  Decompose the NLP into simplified sub-problems u In a multi-level framework with routing I1I1 R 2 =  /a 2 R 3 =  /a 3 R 4 =  /a 4 I4I4 I3I3 I2I2 R1R 

19 OpenAccess extension for 3D design u Define additional 3D info.  Device Layer  Inter-layer via u Provide interface for 3D cad tool  Parameter extraciton  Timing  LVS u Compatible with Cadence Encounter 2D OA AppDef OA Gear Wraper 3D cad toolsCadence

20 Summary u Design Driver  3D Chip Multiprocessor Based on OpenRISC 1200 Based on OpenRISC 1200  NoC Interconnect  RF Reconfigurable Interconnects u Physical Design Flow  Design Flow for 3DM2  Design Flow in Development

THE END Thank You!