1 Lucas-Lehmer Primality Tester Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka

2 Ancient Greeks 300 BC Euclid’s Proof Proved that were an infinite number of Prime numbers that were irregularly spaced

3 How to find Prime Numbers The method used for smaller numbers is called Sieve of Eratosthenes from 240 BC Trial Division is another method for smaller numbers

4 43rd Known Mersenne Prime Found!! December 2005 Dr. Curtis Cooper and Dr. Steven Boone Professors at Central Missouri State University 2 30,402,457 -1

5 rankprimedigitswhowhenreference G92005Mersenne G82005Mersenne G72004Mersenne G62003Mersenne G52001Mersenne SB SB G41999Mersenne SB SB92005

6 Prime Number Competitions Electronic Frontier Foundation $50,000 to the first individual or group who discovers a prime number with at least 1,000,000 decimal digits (awarded Apr. 6, 2000) $100,000 to the first individual or group who discovers a prime number with at least 10,000,000 decimal digits $150,000 to the first individual or group who discovers a prime number with at least 100,000,000 decimal digits $250,000 to the first individual or group who discovers a prime number with at least 1,000,000,000 decimal digits

7 Mersenne Prime Algorithm For P > 2 2 P -1 is prime if and only if S p-2 is zero in this sequence: S 0 = 4 S N = (S N ) mod (2 P -1)

8 Example to Show is Prime 2 7 – 1 = 127 S 0 = 4 S 1 = (4 * 4 - 2) mod 127 = 14 S 2 = (14 * ) mod 127 = 67 S 3 = (67 * ) mod 127 = 42 S 4 = (42 * ) mod 127 = 111 S 5 = (111 * ) mod 127 = 0

9 Computations needed: -Squaring (not a problem…) -Add/Subtract (not a problem…) -Modulo (2^n – 1) multiplication (?) Algorithmic description We knew the computations needed, but how to translate that to gates?

10 Mechanisms behind the math If done with brute force, modulo 2^n-1 could have been ugly. –Would need to square and find the remainder via division. Luckily, for that specific computation, math is on our side, the 2^n-1 constraint saves us from division, as will be seen. A quick search on produced inspiration. Taken from “Efficient VLSI Implementation of Modulo (2^n +- 1) Addition and Multiplication” Reto Zimmermann Swiss Federal Institute of Technology (ETH)

11 Useful Math: Multiplication Just like any other multiplication, a modulo multiplication can be computed by (modulo) summing the partial products. So modulo multiplication is multiplication using a modulo adder.

12 Useful Math: The Modulo Adder The more logic driven math that is the basis of our modulo adder.

13 Last Bits: Modulo Reduction At various points, such as when finding the partial product, the result has to be reduced. There is a nifty way to do that as well.

14 Mod Calc Mod Multiply Count Subtract 2 Block Diagram P Out 16 1 FSM start 1 done 16 Register r4 16 Compare clk 16

15 Mod Multiply Block Diagram Mod add Register 2 p Counter 16 Next Partial Product 16 FSM clk 2 FSM clk P to sub 2 from register

16 Mod Calc Mod Multiply Count Subtract 2 Block Diagram P Out 16 1 FSM start 1 done 16 Register r2 16 Compare clk 16

17 Design Process The Process So far: - Found Mathematical Means (core algorithm) - Found Computational Means (modulo multiplier, adder) From the above, a high level C program was written in a manner that would easily translate to verilog and gates, or at least more standard operations int mod_square_minus(int value, int p, int offset) { int acc, i; int mod = (1 << p) - 1; for(acc=offset, i=0; i<(sizeof(int)*8-1); i++) { int a = (value >> i) & 1; int temp; if (a) { if (i-p > 0) temp = value << (i-p); else temp = value >> (p-i); acc = acc + temp + ((value << i) & ((1 << p) - 1)); } if (acc >= mod) acc = acc - mod; } return acc; } This easily translated into behavorial verilog, and readily turned into a gate- level implementation. Essentially it was written in a more low-level manner.

18 Design Process The rest of the design can simply be thought of as a wrapper for the modulo multiplier. The following slides contain Verilog code that was directly taken from the C code below. module mod_mult(out, itrCount, x, y, mod, p, reset, en, clk); input [15:0] x, y, mod, p; output [15:0] out; input reset, en, clk; wire [15:0] pp, ma0, temp; output [3:0] itrCount; counter mycount(itrCount, reset, en, clk); partial_product ppg(pp, x, y, itrCount, mod, p); mod_add modAdder(out, pp, temp, mod); dff_16_lp partial(clk, out, temp, reset, en); endmodule Top level of multiplier

19 module partial_product(out, x, y, i, mod, p); output [15:0] out; input [15:0] x, y, mod, p; input [3:0] i; wire [15:0] diff1, diff2, added, result, corrected, final; wire [15:0] high, low, shifted, toadd; wire cout1, cout2, ithbith, toobig; sub_16 difference1(diff1, cout1, {12'b0, i}, p); sub_16 difference2(diff2, cout2, p, {12'b0, i}); shift_left shiftL(high, y, diff1[3:0]); shift_right shiftR(low, y, diff2[3:0]); mux16 choose(high, low, shifted, cout1); shift_left shiftL2(toadd, y, i); and16 bigand(added, toadd, mod); fulladder_16 addhighlow(.out(result),.xin(added),.yin(shifted),.cin({1'b0}),.cout(nowhere)); sub_16 correct(.out(corrected),.cout(toobig),.xin(mod),.yin(result)); mux16 correctionMux(.out(final),.high(corrected),.low(result),.sel(toobig)); shift_right ibit({15'b0, ithbit}, x, i); select16 checkfor0(.out(out),.x(result),.sel(ithbit)); endmodule Partial Product Unit w/ modulo reduction

20 module mod_add(out, x, y, mod); input [15:0] x, y, mod; output [15:0] out; wire cout, isDouble, cin; wire [15:0] plus, lowbits, done, mod_bar, check; fulladder_16 add(.out(plus),.xin(x),.yin(y),.cin(cin),.cout()); invert_16 inverter(mod_bar, mod); and16 hihnbits(check, plus, mod_bar); and16 lownbits(done, plus, mod); or8 (cin, check[0], check[1], check[2], check[3], check[4], check[5], check[6], check[7], check[8], check[9], check[10], check[11], check[12], check[13], check[14], check[15]); compare_16 checkfordouble(isDouble, done, 16'b1111_1111_1111_1111); mux16 fixdouble(.out(out),.high(16'b0),.low(done),.sel(isDouble)); endmodule Modulo Adder

21 Final Design Process Notes Lessons learned: Never tweak the schematics without retesting the verilog first. Considering total time spent during this phase, roughly half was on the “core” and the FSM, the rest on the “wrapper”.

22 Road to verification : C 2 Examples of the high-level C implementations: Tyrion:~/Desktop/15525 nstohs$./prime4 7 round 1: (4 * 4 - 2) mod 127 = 14 round 2: (14 * ) mod 127 = 67 round 3: (67 * ) mod 127 = 42 round 4: (42 * ) mod 127 = 111 round 5: (111 * ) mod 127 = 0 2^7-1 is prime Tyrion:~/Desktop/15525 nstohs$./prime4 11 round 1: (4 * 4 - 2) mod 2047 = 14 round 2: (14 * ) mod 2047 = 194 round 3: (194 * ) mod 2047 = 788 round 4: (788 * ) mod 2047 = 701 round 5: (701 * ) mod 2047 = 119 round 6: (119 * ) mod 2047 = 1877 round 7: (1877 * ) mod 2047 = 240 round 8: (240 * ) mod 2047 = 282 round 9: (282 * ) mod 2047 = ^11-1 is not prime

23 Road to verification: Verilog Samples of Verilog Verification output: Partial Product Unit p = ppOut= 56, x= 14, y= 14, i= 2, mod= 127, p= ppOut= 112, x= 14, y= 14, i= 3, mod= 127, p= ppOut= 0, x= 14, y= 14, i= 4, mod= 127, p= ppOut= 0, x= 14, y= 14, i= 5, mod= 127, p= 7 Top Level p = 7 itrOut= x itrOut= 4 itrOut= 14 itrOut= 67 itrOut= 42 itrOut= 111 itrOut= 0 Top Level p = 11 itrOut= x itrOut= 4 itrOut= 14 itrOut= 194 itrOut= 788 itrOut= 701 itrOut= 119 itrOut= 1877 … Tests were either specific tests on important units such as Partial_Product …our top level tests. Note that these are the same results generated from the C code

24 Road to verification: Schematic I Schematic Test of our modular adder Mod 127 = 69

25 Road to verification: Schematic II Plot of the top level output after a single iteration, p=7 Output after a single iteration is 14, the expected value.

26 Road to verification: Schematic III The simulation outputs after a full run, showing the results of all iterations. Simulations start taking a long time. More on that later.

27 Road to verification: Intermission Disk Space required for a full-length schematic test of p=7 : 6 GB Time required for a full-length schematic test of p=7 : 4 hours Disk Space required for a full-length extracted test of p=7 : more Time required for a full-length extracted test of p=7 : longer Disk Space required for a full-length extractedRC test of p=7 : 1 iPod Time required for a full-length extractedRC test of p=7 : T_T Simulations become very demanding and lengthy due to tests needing to be “deep” to be useful. To meet such demands, be sure to use Genuine AMD© CPUs.

28 Road to verification: Layout I 3 words: “the net-lists match” Of course, there is far more to be concerned about. Due to simulator issues, layout simulations were delayed on some major modules. Partial Product Sims In Progress (I Hope)

29 Road to verification: Layout II Top Level layout Sims in Progress

30 Road to verification: Timing Layout Timing Sims in progress Pathmill was useful to help us gauge our critical path, which is one cycle through our modulo multiplier. When run on the top level, a critical path of ns was found. This was in the ballpark relative to our research.

31 Issues extractedRC of partial_product module Registers switch Switching from parallel calculations to series –Transistor count vs. clock cycles Syncing up design between people –Transferring files –Different design styles LONG simulation times Floorplanning –Too much emphasis on aspect ratios and not enough on wiring –Couldn’t decide on one set floorplan

32 Floorplan v1.0 Prime Logic Mod Multiplier Mod Adder FSM Memory

33 Floorplan v2.0

34 Floorplan v3.0

35 Floorplan v4.0

36 Floorplan v5.0

37 Final Floorplan

38 Pin Specs PinType# of Pins Vdd!In/Out1 Gnd!In/Out1 p In16 clkIn1 startIn1 DoneOut1 outOut1 Total-22

39 Initial Part Specs ModuleTransistor Count Area (µm²) Transistor Density FSM mod_p2,4407, mod_add1,2829, partial_product8,67665, count1,6566, sub_167043, Registers1,8486, compare Total16,94297,700.17

40 Final Part Specs ModuleTransistor Count Area (µm²) Transistor Density FSM1521, mod_p1,2808, mod_add1,1685, partial_product7,52054, count1,4248, sub_165762, Registers8966, compare Total13,70286, Aspect Ratio

41 Chip Specs Transistor Count: 13,702 Size: µm x µm Area: 86,621µm² Aspect Ratio: 1.01:1 Density: 0.16 transistors/µm²

42 Final Floorplan

43 Final Floorplan

44 Poly Layer Density: 7.14%

45 Active Layer Density: 8.76%

46 Metal1 Layer Density: 23.86%

47 Metal2 Layer Density: 19.97%

48 Metal3 Layer Density: 11.30%

49 Metal4 Layer Density: 10.34%

50 Conclusions Plan for buffers –Can’t put them in after the fact Your design will change dramatically from start to finish so be flexible Communication is key Do layout in parallel