1. EE 141 Project 2May 8, 20031 Outstanding Features of Design Maximize speed of one 8-bit Division by: i. Observing loop-holes in 8-bit division ii. Taking advantage of given specs iii. Realizing that we are just maximizing raw SPEED iv. Optimizing the Critical Path of Design Summary of Main Results: Critical Path DelayDivide Calculation LatencyClock Period Overall Delay 6.8 ns2(6.8) + 2(.05) = 13.7 ns~7 ns~15 ns NAMES …

2. EE 141 Project 2May 8, 20032 Design Methodology 105/26… …1111001101101001 00011010 11111001111101001 00011010 1111110100101001 00011010 1111111011001001 00011010 1111111110011001 00011010

3. EE 141 Project 2May 8, 20033 Design Methodology  Constraints to take advantage of:  4 total adders available – each iteration requires one add  Optimize for JUST speed - not throughput, power or size  Shifts are very organized – can just perform needed shifts into circuit  Using fancy logic, wiring and all adders can reduce the number of clock cycles per divide

4. EE 141 Project 2May 8, 20034 Architecture - SUE

5. EE 141 Project 2May 8, 20035 Architecture – Output Waveforms

6. EE 141 Project 2May 8, 20036 Proposed Critical Path Important circuits along Critical Path: The critical path is defined entirely by the cascaded 8-bit adder cells. It should be noted that the path is cascading, not Delay = 6.8 ns for adder block

7. EE 141 Project 2May 8, 20037 Critical Path Sizing Methodology STEPS FOR OPTIMIZATION The simplest step is to properly buffer the adder outputs, divisor inputs, and XOR outputs to match the B adder inputs, XOR inputs, and A adder inputs respectively. We used buffer chains of 3-4 inverters and incremental sizing to keep the input/output waveforms consistent between stages. A simple way to make our mirror adder faster was to implement even and odd adder cells, inverting the carry bit back and forth between adjacent cells to remove the inverters necessary to produce correct output carry signals. This also allowed us to remove an inverter from the sum output of the odd adder bit cells taking advantage of the full-adder’s inverting property A final small optimization was made by reversing the A and B inputs on the kill/generate stage of the mirror adder to bring the B inputs closer to the output node. Our design essentially wires the divisor (A) inputs directly to the adders, so divisor data is available before dividend/remainder data in at least 3 of the 4 8-bit adders.

8. EE 141 Project 2May 8, 20038 Output Waveforms of Critical Path

9. EE 141 Project 2May 8, 20039 Trade-Offs of our Design Advantages:  Simplicity of design – trivial control logic  Skip delay of intervening register blocks – only 2 clock cycles Disadvantages:  Bad throughput  Long clock cycle Alternative Designs:  We could speed up the design using pipelining while keeping the same simple control logic and shifting through wiring