# Multiplication and Division

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Multiplication and Division

Division Hardware Structure
Place Dividend in the Remainder Register Divisor 32 bits 32-bit ALU Remainder (Quotient) Shift Left Control 64 bits Write Datapath Unit Control Unit

Done. Shift left half of Remainder right 1 bit
Division Algorithm Start: Place Dividend in Remainder 1. Shift Remainder register left 1 bit Step Remainder Div 1.3b 2.3b 3.3a 4.3a 2. Subtract Divisor register from the left half of Remainder register, and place the result in the left half of Remainder register Remainder < 0 Remainder  0 Test Remainder 3b. Restore original value by adding Divisor to left half of Remainder, and place sum in left half of Remainder. Also shift Remainder to left, setting the new least significant bit to 0 3a. Shift Remainder to left, setting new rightmost bit to 1 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done. Shift left half of Remainder right 1 bit

The following Booth’s Verilog Code is available in the Internet.
You can use some of the coding method, but you can not turn in it as Project 2, the code not meeting Project 2 requirement. module multiplier(prod, busy, mc, mp, clk, start); output [15:0] prod; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [3:0] count; wire [7:0] sum, difference; clk) begin if (start) begin A <= 8'b0; M <= mc; Q <= mp; Q_1 <= 1'b0; count <= 4'b0; end

else begin case ({Q[0], Q_1}) 2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q}; 2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q}; default: {A, Q, Q_1} <= {A[7], A, Q}; endcase count <= count + 1'b1; end Instantiate an adder for addition a subtractor for subtraction This is not an acceptable design alu adder (sum, A, M, 1'b0); alu subtracter (difference, A, ~M, 1'b1); assign prod = {A, Q}; assign busy = (count < 8); endmodule We want a datapath and a control unit to perform signed multiplication based on Booth’s algorithm. The same data path can be used for division by changing the control unit module alu(out, a, b, cin); output [7:0] out; input [7:0] a; input [7:0] b; input cin; assign out = a + b + cin; endmodule

module combination_lock_datapath (Clk, Ld1, Ld2, Ld3, Value, Mux, Equal);
input Clk, Ld1, Ld2, Ld3; input[3:1] Mux, Value; output Equal; reg[3:0] C1, C2, C3; wire[3:0] MuxOutput; assign Equal = (Value == MuxOutput); or C2 or C3 or Mux) begin if (Mux[3] == 1) MuxOutput = C3; if (Mux[2] == 1) MuxOutput = C2; if (Mux[1] == 1) MuxOutput = C1; end Clk) begin if (Ld1) C1 = Value; if (Ld2) C2 = Value; if (Ld3) C3 = Value; endmodule

module combination_lock_controller (Clk, Reset, Equal, Enter, Unlock, Mux);
input Clk, Reset, Equal, Enter; output Unlock; output [3:1] Mux; reg[4:1] state; parameter S1 = 4'b0001; parameter S2 = 4'b0010; parameter S3 = 4'b0100; parameter OPEN = 4'b1000; parameter ERR = 4'b0000; assign Unlock = state[4]; assign Mux[3] = state[3]; assign Mux[2] = state[2]; assign Mux[1] = state[1]; Clk) begin if (Reset) state = S1;

else case (state) S1: if (Enter) begin if (Equal) state = S2; else state = ERR; end else state = S1; S2: if (Enter) begin if (Equal) state = S3; else state = S2; S3: if (Enter) begin if (Equal) state = OPEN; else state = ERR; end else state = S3; OPEN: state = OPEN; ERR: state = ERR; endcase endmodule

A Design Example at gate level: Hamming coder, decoder
A hamming code can correct a single bit error Original Data: D1 D2 D3 D4 D5 D6 D7 D8 Encoded Data: H1 H2 D1 H4 D2 D3 D4 H8 D5 D6 D7 D8 H1 = XOR(D1, D2, D4, D5, D7) H2 = XOR(D1, D3, D4, D6, D7) H4 = XOR(D2, D3, D4, D8) H8 = XOR(D5, D6, D7, D8) original data - Hamming encoder - Encoded data --Noise Channel -Hamming decoder - regenerated original data

Hamming Decoding Scheme
{C8, C4, C2, C1} determines which bit is corrupted. C1 = XOR ( vIn[1], vIn[3], vIn[5], vIn[7], vIn[9], vIn[11]) C2 = XOR ( vIn[2], vIn[3], vIn[6], vIn[7], vIn[10], vIn[11]) C3 = XOR ( vIn[4], vIn[5], vIn[6], vIn[7], vIn[12]) C4 = XOR ( vIn[8], vIn[9], vIn[10], vIn[11], vIn[12])

Design a Hamming Encoder/Decoder using Verilog HDL
module hamEncode (vIn, valueOut); input [1:8] vIn; output [1:12] valueOut; wire h1, h2, h4, h8; xor (h1, vIn[1], vIn[2], vIn[4], vIn[5], vIn[7]), (h2, vIn[1], vIn[3], vIn[4], vIn[6], vIn[7]), (h4, vIn[2], vIn[3], vIn[4], vIn[8]), (h8, vIn[5], vIn[6], vIn[7], vIn[8]); assign valueOut = {h1, h2, vIn[1], h4, vIn[2:4], h8, vIn[5:8]}; endmodule

module hamDecode (vIn, valueOut);
input [1:12] vIn; output [1:8] valueOut; wire c1, c2, c4, c8; wire [1:8] bitFlippers; xor (c1, vIn[1], vIn[3], vIn[5], vIn[7], vIn[9], vIn[11]), (c2, vIn[2], vIn[3], vIn[6], vIn[7], vIn[10], vIn[11]), (c4, vIn[4], vIn[5], vIn[6], vIn[7], vIn[12]), (c8, vIn[8], vIn[9], vIn[10], vIn[11], vIn[12]); deMux mux1 (bitFlippers, c1, c2, c4, c8, 1'b1); xor8 x1 (valueOut, bitFlippers, {vIn[3], vIn[5], vIn[6], vIn[7], vIn[9], vIn[10], vIn[11], vIn[12]}); endmodule module xor8 (xout, xin1, xin2); output [1:8] xout; input [1:8] xin1, xin2; xor a[1:8] (xout, xin1, xin2); endmodule

module deMux (outVector, A, B, C, D, enable);
output [1:8] outVector; input A, B, C, D, enable; and v1 (m12, D, C, ~B, ~A, enable), v2 (m11, D, ~C, B, A, enable), v3 (m10, D, ~C, B, ~A, enable), v4 (m9, D, ~C, ~B, A, enable), v5 (m7, ~D, C, B, A, enable), v6 (m6, ~D, C, B, ~A, enable), v7 (m5, ~D, C, ~B, A, enable), v8 (m3, ~D, ~C, B, A, enable); assign outVector = {m3, m5, m6, m7, m9, m10, m11, m12}; endmodule

module testHam(); reg [1:8] original; wire [1:8] regenerated; wire [1:12] encoded, messedUp; integer seed; initial begin seed = 1; forever begin original = \$random (seed); #1 \$display ("original=%h, encoded=%h, messed=%h, regen=%h", original, encoded, messedUp, regenerated); end hamEncode hIn (original, encoded); hamDecode hOut (messedUp, regenerated); assign messedUp = encoded ^ 12'b 0000_0010_0000; endmodule

Ready: sim original=00, encoded=000, messed=020, regen=00 original=38, encoded=078, messed=058, regen=38 original=86, encoded=606, messed=626, regen=86 original=5c, encoded=8ac, messed=88c, regen=5c original=ce, encoded=79e, messed=7be, regen=ce original=c7, encoded=e97, messed=eb7, regen=c7 original=c6, encoded=f86, messed=fa6, regen=c6 original=f3, encoded=2e3, messed=2c3, regen=f3 original=c3, encoded=a83, messed=aa3, regen=c3 original=5f, encoded=5af, messed=58f, regen=5f original=47, encoded=097, messed=0b7, regen=47 original=89, encoded=709, messed=729, regen=89 original=7e, encoded=1fe, messed=1de, regen=7e original=45, encoded=c85, messed=ca5, regen=45 original=5d, encoded=9bd, messed=99d, regen=5d original=91, encoded=231, messed=211, regen=91 original=6e, encoded=cde, messed=cfe, regen=6e original=8f, encoded=f0f, messed=f2f, regen=8f original=3c, encoded=46c, messed=44c, regen=3c

Design a 4-bit petshop processor with Verilog HDL
Instruction format I[3:2] specifies the pet name I[1:0] specifies the action taken by the pet I[3:2] I[1:0] Description 00 00 dog wag 00 xx dog barks x times 01 00 cat wag 01 xx cat meows x times 10 xx lizard changing colors brown, red, green, yellow 11 xx parrot says xx aloud with xx>0 11 00 petshop is closing

module petshop; event GO; //Opens the petshop. parameter mem_size = 'h0400; //1K of memory parameter PC_init = 'h0000; //Start executing at 0x0000 reg[3:0] M [0:mem_size-1]; //The actual memory reg[7:0] PC; //Program Counter register reg[3:0] I; //Register to hold current instruction reg[3:0] x; //Scratch register `define pet I[3:2] //Corresponds to "pet" field in mcode file `define arg I[1:0] //Corresponds to "arg" field in mcode file

//Main program loop initial begin @GO PC =0; //Initialize Program Counter forever begin : main_loop # //delay for each instruction I = M[PC]; //Fetch instruction PC = PC + 1; //Increment PC case (`pet) //Execute instruction 0: if(`arg==0) \$display("the dog wags its tail."); else for(x=1;x<=`arg;x=x+1) \$display("Bark!"); 1: if(`arg==0) \$display ("the cat wags its tail."); for(x=1;x<=`arg;x=x+1) \$display ("Meow!");

2: case(`arg) 0: \$display("The lizard turns brown."); 1: \$display("The lizard turns red."); 2: \$display("The lizard turns green."); 3: \$display("The lizard turns yellow."); endcase 3: case(`arg) 0: begin \$display("the pet shop is now closing."); \$finish; end 1: \$display ("One!"); 2: \$display ("Two!"); 3: \$display ("Three!"); endmodule

module start; initial begin //\$readmemh("petmem", petshop.M); //\$readmemh is not avaiable in Silos Evaluation copy petshop.M['h0] = 4'b0000; petshop.M['h1] = 4'b0011; petshop.M['h2] = 4'b0101; petshop.M['h3] = 4'b1111; petshop.M['h4] = 4'b1111; petshop.M['h5] = 4'b1101; petshop.M['h6] = 4'b0100; petshop.M['h7] = 4'b1010; petshop.M['h8] = 4'b1000; petshop.M['h9] = 4'b1110; petshop.M['hA] = 4'b1100; -> petshop.GO; end endmodule File:petmem @0 0 @1 3 @2 5 @3 F @4 F @5 D @6 4 @7 A @8 8 @9 E @A C

Silos simulation results
Ready: sim the dog wags its tail. Bark! Meow! Three! One! the cat wags its tail. The lizard turns green. The lizard turns brown. Two! the pet shop is now closing.