Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi.

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Concurrent Test Generation Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Vishwani D. Agrawal Alok S. Doshi Asian Test Symposium (ATS), December 18-21, 2005

Oct. 26, 2005VLSI Design and Test Seminar2 Problem Statement To find the smallest test set to detect all single stuck-at faults in a combinational circuit. An existing solution: –Group faults into fault sets using fault independence –Generate concurrent tests for each group Contribution of this paper: Devise a simulation- based implementation to this solution.

Oct. 26, 2005VLSI Design and Test Seminar3 Outline Introduction Simulation-based Independence Fault Collapsing Simulation-based Concurrent Test Generation Results Conclusions

Oct. 26, 2005VLSI Design and Test Seminar4 Introduction v1v1 v2v2 v3v3... T(F1) T(F2) Problem of finding a minimal test:- Static compaction cannot guarantee optimality. Dynamic compaction is complex. Solution: Target both faults F1 and F2 at the same time to find a single test. Test set for fault F1 Test set for fault F2

Oct. 26, 2005VLSI Design and Test Seminar5 Fault Classification F1 and F2 are equivalent. F1 dominates F2. F1 and F2 are independent. F1 and F2 are concurrently testable. T(F1) = T(F2) T(F1) T(F2) T(F1) T(F2) T(F1)

Oct. 26, 2005VLSI Design and Test Seminar6 Example Circuit a b c d e x y C17 - ISCAS85 Benchmark Circuit 1 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp All faults are Stuck-at-1 type

Oct. 26, 2005VLSI Design and Test Seminar7 Independence Matrix and Graph F C17 - ISCAS85 Benchmark Circuit

Oct. 26, 2005VLSI Design and Test Seminar8 Independence Fault Collapsing 1,8 5,11,7 3,9,2 4,6,10 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9 th VLSI Design and Test Symp., Aug. 2005, pp C17 - ISCAS85 Benchmark Circuit A “similarity” based algorithm [2] collapses the independence graph:

Oct. 26, 2005VLSI Design and Test Seminar9 Simulation-based Independence Fault Collapsing 2 A. S. Doshi and V. D. Agrawal, “Independence Fault Collapsing,” Proc. 9 th VLSI Design and Test Symp., Aug. 2005, pp The independence graph generation procedure [2] requires ATPG. Here we present a new method for graph generation using simulation: –Start with a fully-connected independence graph for an equivalence collapsed fault set. –Simulation of random vectors without fault dropping removes edges between faults detected by the same vector.

Oct. 26, 2005VLSI Design and Test Seminar10 Simulation-based Independence Fault Collapsing bit ALU 301

Oct. 26, 2005VLSI Design and Test Seminar11 Simulation-based Concurrent Test Generation For each group, generate all test vectors for the first fault in the group. –If the number of test vectors for a fault is large, use a subset (e.g., 250 maximum) of vectors. Simulate all faults in the group to select one vector that detects most faults in that group. –If more vectors than one detect the same number of faults within the group, then select the vector that detects most faults outside the group as well.

Oct. 26, 2005VLSI Design and Test Seminar bit ALU Result Group Number Number of faults in group Concurrent Test Vector No test needed

Oct. 26, 2005VLSI Design and Test Seminar13 Results Circuit No. of concurrent groups Concurrent ATPGSingle-fault ATPG VectorsCPU s* AtalantaBest known VectorsCPU s*VectorsCPU s*** 1-b adder 2-b adder 4-b adder 8-b adder 16-b adder 32-b adder 4-b ALU c17 c423 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c ** 52** 16** 84** 106** 44** 84** 37** 12** 73** * Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000

Oct. 26, 2005VLSI Design and Test Seminar14 Conclusions Concurrent test generation produces compact tests when combined with independence fault collapsing. ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits. The concurrent ATPG procedure of this paper gives significantly smaller, and sometimes the optimum, test sets.

Oct. 26, 2005VLSI Design and Test Seminar15 Thank You!