MICE Tracker Front End Progress Tracker Data Readout Basics Progress in Increasing Fraction of Muons Tracker Can Record Determination of Recordable Muons as Functions of Digitization Time and Buffer Level AFE-IIt boards for MICE Hardware Tests of Firmware Modifications –Increased Fraction of Recorded Muons –VLSB Modifications for MICE

Tracker Data Readout Basics 16 Analog Front End II t (AFE-IIt) boards (‘t’ stands for time) Input: Analog charge signals from 512 channels Output: - Digital hit pattern of 512 channels charge amplitudes time amplitudes Each board contains sixteen 32-channel Trigger and Pipeline (TriP-t) chips. – Data from all 16 chips processed in parallel – Within each chip, 32 channels processed in series DFPGA AFPGA ADC TriP-t 1/4 of AFE-IIt board Data from VLPCs X 4 …

Increase number of recorded muons by 1.Decreasing digitization time –Zero suppression –Have TriP-t pipeline collect data during digitization –Remove unnecessary setup cycles 2.Implementing TriP-t analog buffer  Digitization time ≠ dead time. Muon Recording With D0 configuration and 600 kHz muon rate, AFE-IIt boards can record about 136 kHz

Reducing Digitization Time ~ 5724 ns: D0 implementation ~ 5670 ns: Adjust for shorter ISIS bucket period 4536 ns: TriP-t pipeline collect data during digitization 2376 ns: Zero-suppress 30 of 32 TriP-t channels 1836 ns: Reduce zero-suppression time from 2 to 1 cycle ns: Remove cycles from set-up processes. – Assumed muon rate is 600 kHz for average time between muons of 1667 ns. – Clock period taken as 18 ns – Assume 2 out of 32 channels of TriP-t have charge data above threshold We are now starting to reduce the dead time so that it’s comparable to the average time between muons.

Fraction of Recorded Muons Digitization Time (ns) No Buffering 1-level Buffering 2-level Buffering 3-level Buffering 4-level Buffering 600 kHz Muon Rate

Where we were. (Digitization time ~ 5600 ns) Fraction of Recorded Muons Digitization Time (ns) No Buffering 1-level Buffering 2-level Buffering 3-level Buffering 4-level Buffering 600 kHz Muon Rate

No Buffering 1-level Buffering 2-level Buffering 3-level Buffering 4-level Buffering Where we are Fraction of Recorded Muons Digitization Time (ns) 600 kHz Muon Rate

Where we’d like to be Fraction of Recorded Muons Digitization Time (ns) No Buffering 1-level Buffering 2-level Buffering 3-level Buffering 4-level Buffering 600 kHz Muon Rate

AFE-IIt Boards for MICE D0 has all necessary boards for upgrade. We need about 1 or 2 new AFE-IIt boards per week for next couple months. –Michael Wojcik is performing these MICE-specific tests. –MICE requires 16 AFE-IIt boards + 9 spares.

Firmware Modification Overview for Increasing Data Rate Enable TriP-t pipeline to collect data during digitization. Reduce digitization time for channels below threshold (zero-suppression) –6 cycles for channels above threshold –1 cycle for channels below threshold Use TriP-t 4-level analog buffer to enable data collection during digitization. Much progress has been made in modifying the firmware to effect these changes, but Key Question: Will the AFE-IIt boards with the TriP-t chips work with these changes?

Hardware Tests of Increasing Fraction of Recorded Muons Completed TriP-t test stand –2 DG2020 Signal Generators –2 Tektronix P3420 Variable Level Pods –Test board containing TriP-t chip Fed signals into TriP-t test board. First results: TriP-t seems to function with input zero suppression signal sequece. Next steps: - Check output signal integrity to see if input signals were digitized. - Check if buffering events works.

Longer Term Plan for Testing Scheme for Increased Data Rate Test operation of TriP-t test board in various configurations –Nominal firmware before modifications –Various stages of firmware modifications Modify/debug firmware based on what we find.

Data Processing Sequence Collector Field Programmable Gate Array (FPGA) in AFE-IIt board controls the following data processing modes: –Initialization –Acquisition –Digitization –Readout For our scheme to increase data rate, we need to check that –Data transfer between FPGAs is done correctly –Data processing mode sequence works FNAL and RAL groups have modified firmware which accomplish these in simulation. Many checks and tests are needed. Newly commissioned TriP-t test stand at FNAL and imminent AFE-IIt test stands at FNAL and RAL will test TriP-t and AFE-IIt boards.

VLSB for MICE VLSB = VME LVDS SerDes Buffer –VME = Versa Module Europa –LVDS = Low Voltage Differential Signaling –SerDes = Serializer/Deserializer VLSB modules used in –KEK test beam –Tests and diagnostics for D0 readout Main issue: Can VLSB be used in MICE to store tracker data at 600 kHz trigger rate?

VLSB Investigations VLSB triggering tested with AFE-IIt Excel spreadsheets. –We could trigger only one of four banks. –Checked data readout to VLSB after occurrence of different numbers of triggers. (We need to read out all data for each trigger due to variable event size.) –We found out from Fermilab Computing Division VLSB experts that these finding were as expected. Possible tracker data format has been formulated. –21 bit words sent from AFE-IIt boards to VLSB modules –Format shown to Fermilab Computing Division VLSB experts –Format shown to Malcolm –Format to be evaluated by Senerath Galagedera

MICE VLSB Requirements In acquisition mode, VLSB stores data (real and null) every clock cycle. –Can VLSB be set up so that it reading a non-zero word? If so, then VLSB can read in real data and not read in null data? –Can VLSB implement a data fast clear? If so, this would prevent reading stale data. Test stand is being set up to determine if current VLSB modules can do these. If current modules don’t meet MICE requirements, Fermilab Computing Division VLSB experts will modify VLSB firmware. If firmware modifications don’t work, VLSB module will be redesigned. Store data from each spill (~ 600 muons/1 ms) in continuous VLSB memory space –AFE-IIt boards send zeros to VLSB modules between muon triggers. –VLSB overwriting current memory location when receiving a zero word would squeeze wasted memory space between triggers. Ensure that data read out to VLSB is from current trigger (not a stale trigger). –Clearing VLSB memory through VME single-word transfers takes about 0.55 sec. –Fast-clear of VLSB memory would be done in about 0.01 sec.

Summary of Tracker Hardware Tests TriP-t test stand commissioned –Initial tests indicate that running zero-suppression doesn’t stop TriP-t operation. Output signal quality tests to be made soon. –To be tested next: Data buffering Enabling pipeline New FPGA communication works as needed Data processing sequence remains working VLSB test stand set up –Fermilab Computing Division experts will test current modules to see if they can meet MICE requirements. Hardware tests of TriP-t chips and VLSB modules needed to determine if AFE-IIt boards can digitize and readout muon data at ~600 kHz.

Extra Slides

Word Type Definitions (Preliminary) D20-18D17D D D X 110PEVENT SYNC # WORD COUNT X 101PDATA X 100PDATA X 011P DATAX 010P X X VLSB Trigger Word Header Word Data Word Data w/t filler LO Data w/t filler HI Fill Word VLSB Null Word P = parity bitX = Serdes sync bit These 21-bit words form events which encode the tracker data. AFPGA0 Data AFPGA1 Data

P = parity bitX = Serdes sync bit Sample Event X 110PEvent Sync #Word CountX 101 PAFPGA0 Bitmap DATA AFPGA0 Bitmap DATA AFPGA1 Bitmap DATA AFPGA1 Bitmap DATA X 101 PChannel DATA TriP0 time DATA TriP1 time DATA TriP0 charge DATA Trip1 charge DATA FILLER (no hits for AFPGA1) X VLSB trigger word Header word Bitmap words Channel readout AFPGA0 Data AFPGA1 Data