Fast Logic Restructuring Using Node Merging and Node Addition and Removal Yung-Chih Chen 陳勇志 Department of Electrical Engineering Chung Yuan Christian University /10/27

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

Introduction  Node merging is a logic restructuring technique -Replace one node with another node in a logic circuit /10/27 A B A B Circuit size reduction

Introduction  Two nodes can be correctly merged when -they are functionally equivalent, or -their functional differences are never observed at a primary output (PO) Observability Don’t Care (ODC) /10/27

Example n3n3 n1n1 n2n2 n4n4 n5n5 n6n6 n7n7 n8n8 n9n9 n 10 n 12 n 13 n 11 x1x1 x2x2 x3x3 x4x4 n 6 and n 8 are not functionally equivalent Their values only differ when x 3 = 1 and x 2 = x 4 x 2 = x 4 implies n 7 = 0, n 7 = 0 blocks n 8 The functional differences of n 6 and n 8 are never observable n 8 can be replaced with n 6  And-Inverter Graph (AIG) 2011/10/

Problem formulation  Given a target node n t, find other nodes called substitute nodes which can replace n t without changing the circuit’s functionality -Inputs: a circuit and a target node -Outputs: substitute nodes /10/27

Previous works  Satisfiability (SAT)-based methods /10/27 Full observability computation is VERY expensive Random simulation Candidate collection Merger checking ODC computation SAT solving

Previous works  Local ODC computation [1] -Compute local ODC within a bounded-depth k A node is observable when it is observable at the bounded- depth k -CPU time: controllable -Capability: exact when k is ∞, limited to k  Global ODC computation [2] -Compute global but approximate ODC -CPU time: time-consuming -Capability: not limited to local ODC but not exact /10/27 [1] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. Sangiovanni-Vincentelli, “SAT Sweeping with Local Observability Don’t Cares,” in Proc. Design Automation Conf., 2006, pp [2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp

Our method  One sufficient condition for safely merging two nodes -ATPG-based approach  NO random simulation, NO ODC computation, NO candidates, and NO SAT solving -Run time: efficient  Also find functional equivalent and global ODC- based mergers -Capability: competitive /10/27

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

Stuck-at fault test  A stuck-at fault test -A process to find a test vector which generates different values in the fault-free and faulty circuit -A test vector exists → testable; otherwise, untestable  A test vector must activate and propagate the fault effect to a PO -generates n = 1 -propagates n = 1 to a PO /10/27 stuck-at nn

Mandatory assignment (MA)  Given a stuck-at fault, MAs are  unique value assignments to nodes required for a test vector to exist  MAs are necessary for detecting a stuck-at fault Consider n 8 ’s stuck-at 0 fault: n 8 =1, n 4 =0, n 3 =1, n 7 =1, n 2 =1, n 6 =1 are MAs n2n2 n3n3 n4n4 n6n6 n7n7 n8n8 n 11 x2x2 x3x3 x4x /10/27 stuck-at 0

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

Node merging and misplaced wire error  Replacing n t with n s can be considered a misplaced wire error -The wires, w 1 ~ w 3, should be connected with n t instead of n s /10/27 ntnt nsns w1w1 w2w2 w3w3 Correct circuit C ntnt nsns w1w1 w2w2 w3w3 Incorrect circuit C’

detects n t ’s stuck-at 1 fault and generates n s = 1 n s = 0 is necessary for detecting n t ’s stuck-at 1 fault A test vector of a replacement error  To detect a replacement error, a test vector must -1) generates n t ≠ n s, and generates n t = 1 and n s = 0, or generates n t = 0 and n s = 1 -2) propagates the value of n t to a PO ntnt nsns ntnt nsns detects n t ’s stuck-at 0 fault and generates n s = 0 n s = 1 is necessary for detecting n t ’s stuck-at 0 fault /10/27

A sufficient condition  Condition: -n t can be replaced with n s -No test vector can generate n t ≠ n s, and propagate the value of n t to a PO simultaneously -n t can be replaced with INV(n s ) n s = 1 is necessary for detecting n t ’s stuck-at 0 fault, and n s = 0 is necessary for detecting n t ’s stuck-at 1 fault n s = 0 is an MA of n t ’s stuck-at 1 fault n s = 1 is an MA of n t ’s stuck-at 0 fault, and n s = 1 is an MA of n t ’s stuck-at 1 fault n s = 0 is an MA of n t ’s stuck-at 0 fault, and /10/27

Example n1n1 n2n2 n3n3 n4n4 n5n5 n6n6 n7n7 n8n8 n9n9 n 10 n 12 n 13 n 11 x1x1 x2x2 x3x3 x4x4 MAs(n 8 =sa0):{n 8 =1, n 4 =0, n 3 =1, n 7 =1, n 2 =1, n 6 =1} MAs(n 8 =sa1):{n 8 =0, n 7 =1, n 4 =0, n 2 =1, n 3 =0, n 6 =0, n 10 =0} Substitute nodes: n 6, n /10/27

Substitute node identification  Two MA computations are required for each node  MAs(n t =sa0) and MAs(n t =sa1)  It could identify more than one substitute node MAs(n t =sa0) MAs(n t =sa1) nsnsnsns nsnsnsns /10/27

Experimental setup  Within ABC [3] environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU  Two experiments -Substitute node identification -Circuit size reduction Each benchmark is initially optimized by using resyn2, a local rewriting optimization /10/27 [3] Berkeley Logic Synthesis and Verification Group, “ABC: A System for Sequential Synthesis and Verification,”

Substitute node identification CircuitAIG N rep % N sub ratio Time (s) N equ N sub, k>5 i2c pci_spoci systemcdes spi des_area tv systemcaes ac97_ctrl mem_ctrl usb_funct aes_core pci_bridge wb_conmax des_perf average total

Circuit size reduction (1/2) CircuitAIG Our approach SAT-based node merging [4] Nr%Time%Time pci_ i2c dalu C s C i s alu system spi tv s mem_ s ac97_ctrl [2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp

Circuit size reduction (2/2) CircuitAIG Our approach SAT-based node merging [4] Nr%Time%Time systemc usb_f pci_ aes_ b wb_ des_ average total ratio

Summary  We propose a fast ODC-based node merging algorithm -ATPG-based -3.3 substitute nodes x faster  We propose a node merging-based approach for circuit size reduction /10/27 Yung-Chih Chen, Chun-Yao Wang, "Fast Detection of Node Mergers Using Logic Implications", 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009), pp , Nov Yung-Chih Chen, Chun-Yao Wang, "Fast Node Merging with Don’t Cares Using Logic Implications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp , Nov. 2010

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

Node addition and removal  Node addition and removal (NAR) is an extended technique of node merging /10/27 A B A B A B C

Example: node merging and NAR  And-Inverter Graph (AIG) n1n1 n2n2 n3n3 n4n4 a b c d n5n5 n7n7 n6n6 n 5 and n 6 are functionally non- equivalent Their values only differ when n 2 = 1 and a = c a = c implies n 1 = 0, which blocks n 5 The functional differences of n 5 and n 6 are never observable n 5 can be replaced with n /10/27

Example: node merging and NAR  And-Inverter Graph (AIG) n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 There is no substitute node that can replace n 6 The added node n 8 can replace n 6 n 2 can be removed as well n8n8 NAR can complement node merging /10/27

/10/27 Problem formulation  Given a target node n t in a circuit, find a node n a which can safely replace n t after it is added into the circuit -n a is named an added substitute node and driven by two nodes existing in the circuit

Node addition and removal  Extend our prior node-merging method -sufficient conditions for an added node to be an added substitute node  NAR and node merging both perform node replacement -If an added node n a satisfies Condition 1, it is a substitute node, and thus, an added substitute node n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) /10/27

Node addition and removal  We do not iteratively add any one node and then check if it is an added substitute node due to inefficiency /10/27 n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 ? ? ? ? ? ?

Node addition and removal  Identify two existing nodes, n f1 and n f2, which are fanin nodes of an added substitute node n a -Suppose n a = AND(n f1, n f2 ) n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) nana n f1 n f /10/27

/10/27 Experimental setup  Within ABC environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU  Three experiments -Replaceable node identification -Circuit minimization Each benchmark is initially optimized by using resyn2, a local rewriting optimization

Replaceable node identification CircuitAIG Our NM Our NAR N rep % Time (s) N rep % Time (s) i2c pci_spoci systemcdes spi des_area tv systemcaes ac97_ctrl mem_ctrl usb_funct aes_core pci_bridge wb_conmax des_perf average total

Average results for totally 23 benchmarks Average results for totally 23 benchmarks Combine our approach with resyn2 Combine our approach with resyn2 Circuit minimization SAT-based NM Our NM Our NAR Reduction % Time (s) Reduction % Time (s) Reduction % Time (s) average total ratio (Ours+resyn2) x 3 resyn2 x 6 Ours x 6 Reduction % Time (s) Reduction % Time (s) Reduction % Time (s) average total /10/27

/10/27 Summary  We proposed an ATPG-based NAR approach -No random simulation, no candidates, and no SAT solving -Complement the node-merging approach by finding more replaceable nodes  It has a competitive quality and spends much less CPU time, compared to the SAT-based node-merging approach Yung-Chih Chen, Chun-Yao Wang, "Node Addition and Removal in the Presence of Don’t Cares", 2010 ACM/IEEE Design Automation Conference (DAC2010), pp , July (Best Paper Nominee) Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

/10/27 SAT-based bounded sequential equivalence checking  SAT-based BSEC F0F0 G0G0 F1F1 G1G1 F n-1 G n-1 FnFn GnGn PIs S0S0 POs... T=0T=1T=n-1T=n

/10/27  Optimization flow SAT-based bounded sequential equivalence checking MiterUnrolling F0F0 G0G0 PIs POs FFs NM & NAR F’ 0 G’ 0 PIs POs F’ n G’ n PIs POs... NM & NAR SAT solving

SAT-based BSEC facilitation CircuitFFsk Original Simplified Speedup SAT T (s) Total T (s) Ratio Saved T (s) b ss_pcm usb_phy sasc des_area i2c simple_spi s systemcdes s spi b b s b ac97_ctrl average total Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 39

Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion /10/27

Conclusion  We propose two logic optimization methods -ATPG-based node merging Faster than previous SAT-based methods Competitive quality -ATPG-based node addition and removal Enhance node merging -They can be integrated to facilitate SAT-based BSEC /10/27

Thank you /10/27

Node addition and removal  Identify two existing nodes, n f1 and n f2, which are fanin nodes of an added substitute node n a -Suppose n a = AND(n f1, n f2 ) n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) Condition 2: n f1, n f2 … Condition 3: n f1, n f2 … nana n f1 n f /10/27

Condition 2  Condition 2: {n f1 =1, n f2 =1} is in MAs(n t =sa0) nana n f1 n f n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) Condition 3: n f1, n f2 … /10/27

Condition 3  Condition 3: n f2 =0 is in imp({n f1 =1, MAs(n t =sa1)}) -imp({n f1 =1, MAs(n t =sa1)}) is the set of value assignments logically implied by {n f1 =1, MAs(n t =sa1)} Test set for n t =sa1 n f1 =0 n f1 =1 n a =0 n f2 =0 Condition 3 n a =0 n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) /10/27

Condition 3  Condition 3: n f2 =0 is in imp({n f1 =1, MAs(n t =sa1)} ) -imp({n f1 =1, MAs(n t =sa1)}) is the set of value assignments logically implied by {n f1 =1, MAs(n t =sa1)} n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) /10/27

Example  n 6 is a target node to be replaced MAs(n 6 =sa0) n f1 imp({n f1 =1, MAs(n 6 =sa1)}) n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 n 6 =1, n 2 =1, c=1, b=1, d=1, n 3 =1, n 4 =1 Suppose we select n 3 as n f1 n 6 =0, n 3 =1, c=1, b=1, n 2 =0, d=0, n 4 =0 nana /10/27

n a identification flow MAs(n t =sa0) imp({n f1 =1, MAs(n t =sa1)}) n a =AND(n f1, n f2 ) Given a target node n t Select n f1 n f /10/27

Eight types of n a (1/2) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) {n f1 =0, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =0, MAs(n t =sa1)}) {n f1 =1, n f2 =0} in MAs(n t =sa0) n f2 =1 in imp({n f1 =1, MAs(n t =sa1)}) {n f1 =0, n f2 =0} in MAs(n t =sa0) n f2 =1 in imp({n f1 =0, MAs(n t =sa1)}) nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 nana n f1 n f /10/27

Eight types of n a (2/2) {n f1 =1, n f2 =1} in MAs(n t =sa1) n f2 =0 in imp({n f1 =1, MAs(n t =sa0)}) {n f1 =0, n f2 =1} in MAs(n t =sa1) n f2 =0 in imp({n f1 =0, MAs(n t =sa0)}) {n f1 =1, n f2 =0} in MAs(n t =sa1) n f2 =1 in imp({n f1 =1, MAs(n t =sa0)}) {n f1 =0, n f2 =0} in MAs(n t =sa1) n f2 =1 in imp({n f1 =0, MAs(n t =sa0)}) nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 nana n f1 n f /10/27

Circuit size reduction For each node n t Identify substitute nodes and replace n t Identify added substitute nodes and replace n t n t is replaced n t has a fanin driving only n t /10/27