Regular Realization of Symmetric Binary and Ternary Reversible Logic Functions

Abstract We introduce here a new regular structure to realize ternary symmetric functions in reversible logic This idea is very general and applies also to binary logic, quaternary logic and any other radix It should be further investigated if the presented approach can be generalized to fuzzy logic. –Based, on my past experience (Singapure paper with Edmund) I believe that it cannot be applied to classical fuzzy logic, but a (continuous) logic similar to fuzzy logic can be defined to which it can be applied. Because every function is symmetrizable, our method allows to realize arbitrary symmetric function in a completely regular structure of reversible gates with very little “waste of outputs”

Fredkin Gate Fredkin Gate (FG) is the fundamental concept in reversible and quantum computing, the base of everything. It was introduced by Ed Fredkin and Tomasso Toffoli in 1982 in “Conservative Logic”, Intern.J.Theor. Phys., 21, pp Fredkin Gate has been realized in various ways: –optical Cuykendall, R., and McMillin, D, “Control-Specific Optical Fredkin Circuits”, Applied Optics, 26, pp , Shamir, J., Caulfield, H.J., Micelli, W., and Seymour, R.J., “Optical Computing and the Fredkin Gates”, Applied Optics, 25, pp , Picton, P.D., “Opto-Electronic Multi-Valued Conservative Logic”, Int. J. Optical Computing, 2, pp , 1991 –electrical De Vos, U.C. Berkeley, Japanese, polish -Lodz, I will find –mechanical (nano-technology) Perhaps in Drexler book or papers? We have to find –quantum. Smolin, J.A., and DiVincenzo, D.P. “Five Two-Bit Quantum Gates are sufficient to Implement the Quantum Fredkin Gate”, Physical Review A, 53, pp

Multi-Valued Fredkin Gate Multi-Valued Fredkin Gate (MVFG) was introduced by Picton –Picton, P.D., “Modified Fredkin Gates in Logic Design”, Microelectronics Journal, 25, pp , Picton showed that: –The gates are universal –T-gates (which are universal) can be build from MVFGs. –Post literals can be build from MVFGs. –MIN and MAX can be build quite efficiently –Multi-valued SOP (MAX OF MINs) can be build. Thus Picton proved that every MVL circuit can be build using his method and his gates. However, his design has the following disadvantages –the structure is irregular –there are many gates –the delay is long I claim that for symmetric functions the method below gives much better solutions. It is known that every Boolean function can be symmetrized and Alan writes an efficient program for it. Alan can generalize this program to Multi-Valued Logic (MVL). I am sure, although it was not formally proven, that every multi-valued function can be symmetrized. –I suggest that Xiaoyu will prove it using the same method as used by me in paper with Malgorzata (VLSI Design, 1998) Thus, with the proof and new Alan’s algorithm, the method below will allow to realize arbitrary mvl function in a regular structure of reversible gates.

Multi-Valued Fredkin Gate Because our structure is programmable, the byproduct of this research is that we propose for the first time an FPGA for reversible multi-valued logic In future we should experimentally compare this approach to other approaches using software, but I believe now it is enough to publish a theoretical paper, because what we already have is better (from logic synthesis point of view) than published by physicists in the journal papers above mentioned. In future we should have two pieces of software: –Given an arbitrary mvl function F, find its symmetric counterpart FS by repeating some variables. –Realize FS in a proposed below regular structure.

Principles of creating logic synthesis algorithms for Reversible Logic Let us recall that: –In reversible logic wires can cross but in Quantum Logic the wires cannot cross. –In both reversible and Quantum Logic it is not possible to have a fanout larger than 1. –You need a special gate to extend from fanout of 1 to fanout of 2, high fanout needs introducing many such gates which is bad. –You can use constants in inputs or outputs of reversible gates. –Feedback in gate is not allowed –Trivial method is to take any known logic structure from gates and replace every gate with a universal reversible gate. But this generates the “waste of outputs” - a lot of wires that are congesting the layout without any use. This is very bad for future technologies - remember the “curse of wiring” which will dominate future technologies unless cellular-like logic were used –Quantum Logic –Quantum Logic is reversible. So, everything that we will do here will be useful for Quantum Logic as well. I believe these structures are very good for QL because they have no wire overlap. So far in the papers that I read on QL, they are using Fredkin, Toffoli, Margolus, etc binary gates and Square- Root-of-Not gate of Feynman that is the only gate that cannot be realized in classical reversible logic. I believe that we can extend principles of symmetry for complete Quantum Logic so it will include also Square-Root-of-Not gate and many other new gates that I created for QL, but because I do not understand quantum mechanics, may be these gates are nonsensical physically and exist only in theory.

Principles of creating logic synthesis algorithms for Reversible Logic Smart method of synthesis with reversible gates should: –Do not create many outputs of gates –Re-use these outputs as inputs in other gates –Apply re-usability properties of these common subfunctions - I believe that symmetry introduced here is only one of such proporties and we will fine more of them –Be generally applicable –(I believe) Use regularity and group/field/linear algebra properties that are so useful in binary logic.

Multi-valued Fredkin Gate MVFG is described by equations: P = A Q = B R = C if A < B else R = D S = D if A < B else S = C ABCDABCD PQ RSPQ RS >=

Use Multi-valued Fredkin Gate to create MIN/MAX gate ABCDABCD PQRSPQRS >= A BCDA BCD PQ RSPQ RS MIN(A,B) MAX(A,B) Feedback not allowed - so it is a bad gate Similarly fan-out is not allowed

Good Use of two Multi-valued Fredkin Gates to create MIN/MAX gate AB01AB01 >= MIN(A,B) MAX(A,B) >= MIN(A,B) MAX(A,B) Min/max gate MAX(A,B) MIN(A,B) Max/min gate

MAX/MIN gate in binary case MAX(A,B) MIN(A,B) Max/min gate f2 f1 f6 f3 A B

What gates we need to realize every symmetric function of two binary variables? All symmetric binary function of polarity 1,1 There are two NPN classes of (symmetric) functions for binary AND and EXOR NPN Classes for binary AND class of NPN EXOR class of NPN 1

What gates we need to realize every symmetric function of two binary variables? f1 f2 f3 f4 f5 f6 1 f2 f1 f6 f3 A B 1 f5 0 f4 A B

Property Even without ability of realizing any symmetric function of two variables one can realize arbitrary symmetric function of any number of variables: by building a regular structure from MAX/MIN gates and next applying EXORing operations to find single-value symmetric coefficients and next OR gates to sum them Regular symmetric structure EXOR level OR level

Every Symmetric Function can be composed of MIN/MAX gates in case of binary logic:Example for three variables MAX(A,B) MIN(A,B) Max/Min gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) Indices of symmetric binary functions of 3 variables =A+B =A*B AB C C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) 1

Every single index Symmetric Function can be created by EXOR-ing last level gates of the previous regular expansion structure MAX(A,B) MIN(A,B) Max/Min gate A B C S 1,2,3 (A,B,C) S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) 1 S 1 (A,B,C) S 2 (A,B,C)

Example for four variables MAX(A,B) MIN(A,B) Max/Min gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) Max/Min gate D MIN(A,B) MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4 (A,B,C) MIN(A,B,C,D) = A*B*C*D = S 4 (A,B,C,D) S 3,4 (A,B,C,D) S,2.3.4 (A,B,C,D)

Example for four variables, EXOR level added MAX(A,B) MIN(A,B) Max/M in gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) Max/M in gate D MIN(A,B) MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4 (A,B,C) MIN(A,B,C,D) = A*B*C*D = S 4 (A,B,C,D) S 3,4 (A,B,C,D) S,2.3.4 (A,B,C,D) S 3 (A,B,C,D) S 4 (A,B,C,D) S 2 (A,B,C,D) S 1 (A,B,C,D) Now it is obvious that any multi-output function can be created by OR-ing the outputs of EXOR level

Now we generalize for Reversible Logic MAX(A,B) MIN(A,B) Max/M in gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) Max/M in gate D MIN(A,B) MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4 (A,B,C) MIN(A,B,C,D) = A*B*C*D = S 4 (A,B,C,D) S 3,4 (A,B,C,D) S,2.3.4 (A,B,C,D) S 3 (A,B,C,D) S 4 (A,B,C,D) S 2 (A,B,C,D) S 1 (A,B,C,D) S 3,4 (A,B,C,D) S 2,3,4 (A,B,C,D) Denotes fan-out gate Denotes Feynman (controlled NOT) gate

Theorem for Binary Reversible Logic MAX(A,B) MIN(A,B) Max/M in gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) Max/M in gate D MIN(A,B) MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4 (A,B,C) MIN(A,B,C,D) = A*B*C*D = S 4 (A,B,C,D) S 3,4 (A,B,C,D) S,2.3.4 (A,B,C,D) S 3 (A,B,C,D) S 4 (A,B,C,D) S 2 (A,B,C,D) S 1 (A,B,C,D) S 3,4 (A,B,C,D) S 2,3,4 (A,B,C,D) Theorem 1 : Every positive unate (symmetric ) function of 2 variables can be realized in 1 gate Every positive unate function of 3 variables can be realized in 1+2 gates Every positive unate function of 4 variables can be realized in gates Every positive unate symmetric function of n variables can be realized in n-1 = n(n-1)/2 MAX/MIN gates

Theorem for Binary Reversible Logic MAX(A,B) MIN(A,B) Max/M in gate A B C MAX(A,B,C) = (A+B)+C = S 1,2,3 (A,B,C) MIN(A,B,C) = (A*B)*C = S 3 (A,B,C) =A+B =A*B C(A+B) S 2,3 (A,B,C) = (A*B) + C(A+B) Max/M in gate D MIN(A,B) MAX(A,B,C,D) = A+B+C+D = S 1,2,,3,4 (A,B,C) MIN(A,B,C,D) = A*B*C*D = S 4 (A,B,C,D) S 3,4 (A,B,C,D) S,2.3.4 (A,B,C,D) S 3 (A,B,C,D) S 4 (A,B,C,D) S 2 (A,B,C,D) S 1 (A,B,C,D) S 3,4 (A,B,C,D) S 2,3,4 (A,B,C,D) Theorem 2 : Every single index totally symmetric function of n variables can be realized in n(n-1)/2 MAX/MIN gates, n-2 fan-out gates and n-1 Feynman gates. Theorem 3 : Every single-output totally symmetric function of n variables can be realized in n(n-1)/2 MAX/MIN gates, n-2 fan-out gates, n-1 Feynman gates and XXX? OR gates. NOT FINISHED HERE

Using MIN/MAX gates MIN(A,B) MAX(A,B) Min/max gate Min/Max gate will become now our main building block ABAB B A 012A 012 Map of MIN gate Map of MAX gate Symmetric ! A 012A 012 Monotonic! 2,2 1,2 1,1

MIN/MAX gates cannot realize every symmetric function of two variables B A 012A 012 Map of MODSUM = Galois Addition gate Symmetric ! B Map of Galois Multiplication gate Symmetric ! A 012A 012 NOT-Monotonic! Non-Monotonic! 1,2 0,1 Latin Square! NOT Latin Square!

What gates we need to realize every symmetric function of two variables? B A 012A 012 2,2 1,2 1,1 0,1 0,0 0, All symmetric binary function of polarity 1,1 And how it will be for ternary? There are two NPN classes of symmetric functions for binary AND and EXOR