1. REVERSIBLE LOGIC SYNTHESIS

2. Overview of the Presentation 1. Introduction 2. Design of a Reversible Full-adder Circuit

3. Part 1 Introduction

4. The gate/circuit that does not loose information is called reversible. What is Reversible Logic / Reversibility ? Input Vector I v =( I i,j, I i+1,j, I i+2,j, …, I k-1,j, I k,j ) Output Vector O v =( O i,j, O i+1,j, O i+2,j, …, O k-1,j, O k,j ) For each particular vector j I v  O v Def n 1: A Reversible circuit has the facility to generate a unique output vector from each input vector, and vice versa.

5. What is Reversible Logic / Reversibility ? (cont.) Def n 2: Reversible are circuits in which the number of inputs is equal to the number of outputs and there is one-to-one mapping between vectors of inputs and outputs. Reversible Gate i i i i i 1 2 3 K-1 K O O O O O 1 2 3 K A gate with k inputs and k outputs is called k*k gate.

6. Difference Between Reversible Gate and Irreversible Gate Truth Table For Irreversible EXOR Logic InputsOutput ABC = A B 000 011 101 110

7. Difference Between Reversible Gate and Irreversible Gate (cont.) Truth Table For Reversible EXOR Logic (Feynman Gate) InputsOutput ABP=AQ = A B 0000 0101 1011 1110

8. It has been proved ( by Bennett and Landauer [1]) that, “losing information in a circuit causes losing power. Information lost when the input vector cannot be uniquely recovered from the output vector of a combinational circuit”. The gate/ circuit does not loose information is called reversible. Motivation Towards Reversible Gate

9. Garbage Bit Every gate output that is not used as input to other gate or as a primary output is called garbage. The unutilized outputs from a gate are called “garbage”. Heavy price is paid off for every garbage output. A B P = A * Q = A B

10. Some Popular Reversible Gates P = A ' A Not Gate AP 01 10 1 x 1 Not Gate

11. Some Popular Reversible Gates (cont.) A B P = A Q = A B Feynman Gate AB PQ 00 00 01 01 10 11 11 10 2 x 2 Feynman Gate (CNOT Gate) [2]

12. Some Popular Reversible Gates (cont.) A B Toffoli Gate C P = A Q = B R = AB C ABC PQR 000 000 001 001 010 010 011 011 100 100 101 101 110 111 111 110 3 x 3 Toffoli Gate [3]

13. Some Popular Reversible Gates(cont.) A B Fredkin Gate C P = A Q = A ' B AC R = A ' C AB ABC PQR 000 000 001 001 010 010 011 011 100 100 101 110 110 101 111 111 3 x 3 Fredkin Gate [4]

14. Some Popular Reversible Gates(cont.) A B New Gate C P = A Q = AB C R = A'C' B' ABC PQR 000 000 001 011 010 001 011 010 100 101 101 111 110 110 111 100 3 x 3 New Gate (Khan Gate) [5]

15. Some Popular Reversible Gates(cont.) A B Peres Gate C P = A Q = A B R = AB C ABC PQR 000 000 001 001 010 010 011 011 100 110 101 111 110 101 111 100 3 x 3 Peres Gate[6]

16. Different Modes of Feynman Gate 0 B P = 0 Q = B Feynman Gate All possible cases in 2 x 2 Feynman Gate A as control input Output B as control input Output PQPQ 00B 0AA 11 B'B' 1AA' 1 B P = 1 Q = B ' Feynman Gate A 0 P = A Q = A Feynman Gate A 1 P = A Q = A ' Feynman Gate

17. Realizations of Irreversible Gates Using Reversible Gates A B Toffoli Gate 0 P = A Q = B R = AB 0 = AB InputOutput ABC 000 010 100 111 A B AND GATE C = AB AND GATE

18. Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 1 P = A Q = B R = AB 1 = AB InputOutput ABC 001 011 101 110 A B NAND GATE C = AB NAND GATE

19. Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 1 P = A Q = B R = A B 1 =A B =A + B InputOutput ABC 000 011 101 111 A B OR GATE C = A + B OR GATE

20. Realizations of Irreversible Gates Using Reversible Gates(cont.) A B Toffoli Gate 0 P = A Q = B R = A B 0 = A + B InputOutput ABC 001 010 100 110 A B NOR GATE C = A + B NOR GATE

21. Reversible Network Structure

22. The main rules for efficient reversible logic synthesis Use as many outputs of every gate as possible, and thus minimize the garbage outputs. Do not create more constant inputs to gates that are absolutely necessary. Avoid leading output signals of gates to more than one input( Fanout). Don’t use any feedback loop; it is strictly restricted. Use as less number of reversible gates as possible to achieve the goal. The main rules for efficient reversible logic synthesis

23. Part 2 Design of a Reversible Full-adder Circuit

24. Input Output ABC in SumC out 00000 00110 01010 01101 10010 10101 11001 11111 Design of a Reversible Full-adder Circuit Sum=A B C Carry=AB + BC + CA =AB BC CA

25. Design of a Reversible Full-adder Circuit(cont.) Sum=A B C Carry=AB + BC + CA =AB BC CA A B EXOR GATE A B EXOR GATE Sum AND GATE AND GATE AND GATE C EXOR GATE EXOR GATE Carry

26. Design of a Reversible Full-adder Circuit Sum=A B CCarry=AB + BC + CA =AB BC CA A B P = A Q = A B Feynman Gate Q = A B C = Sum Feynman Gate P = A B C

27. Design of a Reversible Full-adder Circuit (cont.) Sum=A B C Carry =AB BC CA A B Toffoli Gate 0 P = A Q = B R = AB B C Toffoli Gate 0 P = B Q = C R = BC C A Toffoli Gate 0 P = C Q = A R = CA P = AB Q = AB BC Feynman Gate P = AB BC Q = AB BC CA= Carry Feynman Gate

28. Design of a Reversible Full-adder Circuit (cont.) Sum=A B CCarry= =AB BC CA = (A C)B CA A B Toffoli Gate 0 A B AB C Toffoli Gate A B C (A C)B CA = Carry A A B Feynman Gate P = A B Q = A B C = Sum Feynman Gate

29. Three Gates & Three Garbage outputs [5] Four Gates & Two Garbage outputs [7] Existing Reversible Full-adder Circuits

30. Two Gates & Two Garbage outputs Three Gates & Two Garbage outputs Proposed Reversible Full-adder Circuits

31. Comparative Results Gates Garbage Outputs Existing 1 42 Existing 2 33 Proposed 1 32 Proposed 2 22

32. Input Section Output Section ABC in Sum (S)C out 0011 0 0101 0 1001 0 Theorem: A reversible full-adder circuit can be realized with at least two garbage outputs

33. A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) Input Section Output Section ABC in SC out G 1 0011 0 0 01010 0 10010 1

34. A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) A reversible full-adder circuit can be realized with at least two garbage outputs (cont.) Input Section Output Section ABC in SC out G1G1 G2G2 00110 00 0101 0 01

35. References [1] C. H. Bennett. Logical reversibility of computation, IBM J. Research and Development, 17:pp. 525-532, November 1973. [2] R. Feynman, Quantum Mechanical Computers, Optical News (1985) 11-20. [3] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980). [4] E. Fredkin, T Toffoli, Conservative Logic, International Journal of Theor. Physics, 21(1982), pp.219-253. [5] Md. M. H Azad Khan, Design of Full-adder with Reversible Gates, International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp 515-519, 2002. [6] Peres, A., Reversible Logic and Quantum Computers, Physical Review A, 32: 3266- 3276, 1985. [7] A. Mishchenko and M. Perkowski. Logic synthesis of reversible wave cascades. International Workshop on Logic Synthesis, pages 197-202, June 2002.

36. The End REVERSIBLE LOGIC SYNTHESIS