1. ECE 352 Digital System Fundamentals
Multiplexers
In this presentation, we will discuss a type of logic block we use very often in digital design: the multiplexer.

2. Multiplexers (Muxes)
Selection: based on the select inputs, choose one from several data inputs to drive an output
Output is equal to one of the data inputs
Select inputs indicate which data input
Typically: n select lines, 2n data input lines
Output
Data Inputs and Labels
Select Input
A multiplexer, or “mux” for short, allows us to implement selection. We set the value of the select inputs in order to choose which data input will drive the output. A multiplexer with n select lines normally has 2^n data inputs. The data inputs are labeled with the select code that will cause that input to be selected.
So, if the select input is 0, the value of the signal on data input 0 will be replicated at the output of the mux. On the other hand, if the select input is 1, the value of the signal on data input 1 will appear at the output.
There are different sizes of muxes that we normally describe as “K-to-1”, where K is the number of data inputs, and the mux has 1 output. The structure shown here would be called a 2-to-1 mux.

3. Select Inputs and Labels
Multiplexer Labeling
Data inputs must be labeled to indicate which is selected for a given select value
Select inputs must be labeled so we know the ordering of bits within the select value
Exception: if there is only one select bit
The labeling on muxes is critical to understanding how they work. Data inputs must always be labeled to know which will be selected for a given select value. If there is more than one select bit, the select bits must be labeled to indicate the bit order for interpreting the select value.
Data Inputs and Labels
Select Inputs and Labels

4. Multiplexer Structure
Can always build things by understanding their truth tables and then building the logic functions…
2:1 multiplexer with 1-bit select signal S
Y = S·D1 + S ·D0
4:1 multiplexer with 2-bit select S Y
One way to construct a mux is to create a truth table, and then use the techniques we’ve already learned to determine the minimal implementation.
Here we show sum-of-products implementations for both a 2-to-1 mux and a 4-to-1 mux. Note that in each function, we have terms for each possible combination of select input values.
= S1·S0·D3
+ S1· S0 ·D2
+ S1 ·S0·D1
+ S1 · S0 ·D0

5. Multiplexer Logic Function
The two-level logic function for any mux output Y is really quite easy to remember
Write an OR of all minterms of the select inputs
AND each minterm with the corresponding data input
Example: An 8-to-1 mux has a 3-bit select input S = S2S1S0
The logic for a multiplexer is very regular, so it is actually quite easy to write down a Boolean function for it without drawing a gate diagram. Just write an OR of all minterms of the select input(s), and then AND each minterm with the corresponding data input.
Let’s use an 8-to-1 mux to illustrate this. An 8-to-1 mux has a 3-bit select signal, which we will label S2 though S0.
First, we write all minterms in shorthand form ANDed with the corresponding data input. You can probably skip this step – we just did it here to show that the minterm index and the data input index (which corresponds to its label on the multiplexer symbol) should match for each term. Next, expand each shorthand minterm to create a 2-level sum-of-products logic function for the multiplexer. The logic for any size mux can easily be expressed using the same method.

6. Other Ways To Build Muxes
Decode select signals into individual enables for each data input
Build larger muxes using smaller muxes
Repeated refinement of the selection code
There are other ways to build multiplexers besides using a 2-level function.
In the example at left, we use a decoder to generate an individual enable signal for each select code, then use AND gates feeding an OR to allow only the selected data input to propagate to the output. Note that this corresponds to ANDing the minterms with the corresponding data input.
In the example at right, we show how a hierarchy of smaller muxes can implement a larger mux. The two muxes on the left each choose an input based on the least significant bit of the select code, and then the mux on the right chooses between those two based on the most significant bit of the select code. Let’s look at this particular example in more depth.
First-level muxes each choose an input based on select bit 0, select bit 1 chooses between the results

7. Hierarchical Mux ExampleD3
 D1 D1
Suppose the select code applied to the hierarchical mux was binary 01. S0 is 1, so the upper mux chooses D3 and the lower mux chooses D1. Since S1 is 0, the output mux chooses D1. The index of the chosen data input matches the value of the select, so this is correct multiplexer behavior.
1 
0 

8. Concept: Value-Fixing
Can set one or more inputs of a logic circuit to a constant (fixed) value (meaning, 0 or 1)
We might do this to make the logic circuit behave in a particular way
Example: set one input of a 2-input XOR gate to 1 to make the XOR act like an inverter
Example: set one input of a 3-to-8 decoder to 0 to make the 3-to-8 decoder act like a 2-to-4 decoder
Need to make sure to use the correct 4 outputs based on which input was set to 0!
Example: implement a logic function with a multiplexer by fixing multiplexer data inputs
This is how the FPGAs used in this class implement logic
We often use value-fixing in conjunction with multiplexers and other logic. It means just what it sounds like – setting an input of a logic circuit to a constant 1 or 0. We do this to refine the behavior of an existing circuit to match our needs, instead of designing an entirely new circuit.
For example, if we need an inverter, but we only have an XOR, we can set one of the XOR inputs to 1. The XOR then acts like an NOT of the other input.
We could also fix one of the inputs of a 3-to-8 decoder to 0 (or 1), so that it behaves like a 2-to-4 decoder.
Another common use of value-fixing is to use a multiplexer to implement a logic function. We connect the function inputs to the mux’s select inputs, then value-fix the data inputs to produce the needed behavior. In this class, we will use devices called field programmable gate arrays, or FPGAs, to implement logic functions using this idea. We’ll discuss FPGAs in more depth in a later video. For now, let’s look at an example of implementing a logic function with a multiplexer and value-fixing.

9. Example: Logic With Muxes
B∙1 + B ∙1 = 1
1 
0 
Truth Table 1
A∙1 + A ∙B
= A + B B
In this example, we have a 4-to-1 mux that happens to be constructed from 2-to-1 muxes. We can use a 4-to-1 mux and value-fixing to implement any function of two variables, because the mux has two select inputs. In this case, we will use it to implement Y = A + B.
We apply the circuit inputs to the mux select signals. Based on the values of A and B, the mux output will be one of the four data inputs. On each data input, we put the value we want the output to be for the corresponding select value. This means that each data input represents one row of the truth table – the row numbered the same as the data input index. In this case, we can see that the data inputs have been value-fixed to match the truth table for the OR function, with the output for row 0 of the truth table connected to D0, and the output for row 3 connected to D3.
Now, let’s figure out algebraically how the mux implements this function. The upper mux output is always 1, since both data inputs are 1. We would arrive at the same conclusion by writing the logic function for a 2-to-1 mux and simplifying. The lower mux output is always B, but this may not be as obvious. However, writing the mux function and simplifying confirms it. Now we write the function for the output mux, simplify, and verify that we have in fact implemented A + B. We can extend this idea to larger functions by using larger muxes – for this approach, the mux must have at least as many select inputs as the function has variables.
A 
B 
Function Inputs
B∙1 + B ∙0 = B

10. Example: Logic With Muxes
F = A   B  C + A  B + A B  C
A B C F
 C C
 1 F 1
 0 C
We can also implement any function of N variables using a mux with N-1 select inputs and a single inverter. In this case, we connect all but one function variable to the select inputs, and then look at the truth table to see the relationship between the remaining function variable and the required output.
In this example, we have connected A and B to the select inputs. Then, for each pair of truth table rows with the same A and B values, there are only four possible relationships between input C and the output F.
In the first two rows where A and B are both 0, F is equal to C, so we apply C to data input 0. In the next two rows, the output is 1, so we value-fix data input 1 to 1. In the next two rows, the output is 0, so we value-fix data input 2 to 0. In the last two rows, we see that F is /C, so we apply /C to data input 3. That is why we needed the inverter.
With this method, we can use a smaller multiplexer to implement our logic functions. Remember that a multiplexer with one fewer select input isn’t just a little smaller, it’s less than half the size!
 C A B
Identify what function is for each set of AB values

11. ECE 352 Digital System Fundamentals
Multiplexers
Muxes are one of the fundamental logic constructs that we’ll use again and again in digital circuit design – you’ll want to be very familiar with them.
This concludes our video on multiplexers.