Download presentation

1
**Design of Regular Quantum Circuits**

4/17/2017 Design of Regular Quantum Circuits Regular circuit = tile-based circuit

2
REVERSIBLE LOGIC

3
**Reversible Permutative logic Gates and Circuits**

4/17/2017 Reversible Permutative logic Gates and Circuits A logic gate is reversible if Each input is mapped to a unique output It permutes the set of input values A combinational logic circuit is reversible if it satisfies the following: Has only one Fanout, Uses only reversible gates, No feedback path, has as many input wires as output wires, and permutes the input values.

4
**Basic Reversible Gates**

4/17/2017 Basic Reversible Gates NOT gate Controlled-NOT or Feynman gate a b a c

5
**Basic Reversible Gates**

4/17/2017 Basic Reversible Gates Toffoli gate (Controlled-Controlled NOT gate) a b c a b f

6
**Basic Reversible Gates**

4/17/2017 Basic Reversible Gates Swap gate Implementation of Swap gate using controlled-NOT Write equations of intermediate state

7
**Basic Reversible Gates**

4/17/2017 Basic Reversible Gates Fredkin gate (Controlled SWAP gate) a b c a f g

8
**Algorithms for Synthesis of Reversible Logic Circuits**

4/17/2017 Algorithms for Synthesis of Reversible Logic Circuits I have given adequate background on reversible logic gates, lets explore the algorithms for synthesis of reversible logic circuits

9
**Popular Algorithms for Synthesis of Reversible Logic Circuits**

4/17/2017 Popular Algorithms for Synthesis of Reversible Logic Circuits MMD: Transformation based Gupta-Agrawal-Jha: PPRM based Mishchenko-Perkowski: Reversible wave cascade Kerntopf: Heuristics based Wille: BDD based synthesis I will describe in detail PPRM based algorithm in next few foils and then we will discuss limitations of these algorithm and how our lattice based synthesis algorithm is better compared to these algorithms.

10
**reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS**

11
**IDEA: use reed-mulLER EXPANSION IN SYNTHESIS OF REVERSIBLE CIRCUITS**

A New Representation is Reed-Muller Expansion (Positive Polarity Reed-Muller). This idea appeared for the first time in paper of Aggrawal and Jha, this paper was a competitor to MMD algorithm. Now we design a new algorithm which takes into account multi-level expansion for reversible circuits.

12
**Example of Agrawal-Jha Algorithm**

4/17/2017 Example of Agrawal-Jha Algorithm c b a co bo ao PPRM form for each output in terms of Input variables are given as follows and node is created Reversible function specification is given as a truth table shown here Output c0, b0 and a0 are derived using EXORCISM-2 developed at PSU and parent node is created

13
**Agrawal-Jha Algorithm (cont..)**

4/17/2017 Parent node is explored by examining each output variable in the PPRM expansion. Factors are searched in the PPRM expansions that do not contain the same input variable. For example in the expansion below appropriate terms are “c” and “ac” The substitution is performed as In this example OR

14
**Agrawal-Jha Algorithm (cont..)**

4/17/2017 Agrawal-Jha Algorithm (cont..)

15
**Agrawal-Jha Algorithm (cont..)**

4/17/2017 Agrawal-Jha Algorithm (cont..) New nodes are created based on substitution

16
**Next stage of Aggrawal-Jha algorithm**

4/17/2017 Next stage of Aggrawal-Jha algorithm

17
**Next stage of Aggrawal-Jha algorithm**

4/17/2017 Next stage of Aggrawal-Jha algorithm

18
**Solution found by the Aggrawal-Jha algorithm**

4/17/2017 Solution found by the Aggrawal-Jha algorithm

19
**Problem with Current Synthesis Approaches**

4/17/2017 Problem with Current Synthesis Approaches Common problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations. High Quantum cost of Toffoli gates with many inputs. Synthesize only reversible functions, not Boolean functions that is not reversible.

20
**Quantum Cost of 4x4 Toffoli Gate**

4/17/2017 Quantum Cost of 4x4 Toffoli Gate Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V+.

21
**CREATING QUANTUM ARRAY FROM LATTICE**

22
**Expansions Rules for Lattice DIAGRAAMS**

4/17/2017 Expansions Rules for Lattice DIAGRAAMS Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion. Positive Davio Lattice is created by performing joining operation for neighboring cells at every level. Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them.

23
**Creating Quantum Array from Lattices**

4/17/2017 On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates. Next I present unique method to create Quantum Array from Positive Davio Lattice. The same approach can be used for other Lattices.

24
**Creating Positive Davio Lattice**

4/17/2017 Creating Positive Davio Lattice Each node represents pDv cell.

25
**Creating Quantum Array from Positive Davio Lattice**

4/17/2017 + c 1 + + 1 d d 1 + + 1 1 + b b + + 1 a 1 1 1 1 a a 1 + 1 1 1 d 1

26
**Quantum Array Representation**

4/17/2017 Quantum Array Representation a b c d d garbage a 1 Å garbage 1 ad 1 Å garbage 1 b ab 1 Å garbage 1 a abd b Å bd d a b Å garbage a bcd cd ac bc abd ad db 1 Å 1 function ad abd db 1 Å

27
**Quantum Array Representation**

4/17/2017 Quantum Array Representation a b c d d garbage a 1 Å garbage 1 ad 1 Å garbage 1 b ab 1 Å garbage 1 We are adding gasbags but it is little cost since our function was not a reversible function to start with and we use only 3x3 Toffoli gate Add foil for Toffoli gate built from controlled-V and controlled-V hermitian Talk about optimization a abd b Å bd d a b Å garbage a bcd cd ac bc abd ad db 1 Å 1 function ad abd db 1 Å

28
**Creating Positive Davio Lattice**

4/17/2017 Creating Positive Davio Lattice Each node represents pDv cell.

29
**Quantum Array Representation**

4/17/2017 Quantum Array Representation

30
**Advantages of Lattice to QA**

4/17/2017 Advantages of Lattice to QA Reversible circuit synthesized with only 3x3 Toffoli gates. Generates reversible circuit for any ESOP. Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates.

31
**Calculating Single-Output Shannon Lattice for Completely Specified Boolean Function.**

32
**Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.**

33
**Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Function.**

34
**DIPAL GATES, DIPAL GATE FAMILIES AND THEIR ARRAYS**

35
**Representation of pdv cell as a toffoli gate**

4/17/2017 Representation of pdv cell as a toffoli gate

36
**Development of Dipal gate**

4/17/2017 a b c f Å = Shannon cell Dipal cell representation with reversible gates Dipal gate is a reversible equivalent of Shannon cell There are 23! = 8! = x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose. Find the reversible counterpart of well-known structures BDD, Lattices, KFDD Show Dipal cell is between Toffoli and Fredkin

37
**Development of Dipal gate (cont..)**

4/17/2017 Development of Dipal gate (cont..) a b c f Å = Shannon cell with negative variable Dipal cell with negative variable represented with reversible gates

38
**Development of Dipal gate**

4/17/2017 a b c f Å = Shannon cell Dipal cell representation with reversible gates Dipal gate is a reversible equivalent of Shannon cell There are 23! = 8! = x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.

39
Dipal gate truth table c b a 1 input output 1 2 6 3 5 4 7

40
**Dipal gate unitary matrix**

000 001 010 011 100 101 110 111

41
**Variants of Dipal gates**

This is called a Dipal Gate Family General view of Dipal Family Gate

42
EXPERIMENTAL RESULTS

43
**Results with Pdv Lattice and comparison with MMD and AJ results**

Benchmark #Real inputs #Garbage inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ 2to5 5 4 31 107 0.12 15 20 100 rd32 3 1 8 < 0.01 rd53 11 39 16 75 13 116 3_17 10 21 6 12 14 6sym 34 150 0.37 62 NA 5mod5 58 90 91 4mod5 18 ham3 7 9 xor5 Xnor5 decod24 2 30 Cycle10_2 180 860 27.9 19 1198 ham7 22 0.10 23 81 24 68

44
**Results with Pdv Lattice and comparison with MMD and AJ results (cont**

Benchmark #Real inputs #Garbage inputs #Gates Lattice Cost Lattice CPU time Lattice #Gates DMM Cost DMM #Gates AJ Cost AJ graycode6 6 5 < 0.01 graycode10 10 9 graycode20 20 19 nth_prime3_inc 3 4 nth_prime4_inc 16 48 12 58 nth_prime5_inc 29 91 0.22 26 78 alu 2 17 18 114 4_49 52 0.04 13 61 hwb4 28 63 15 35 hwb5 24 96 1.2 104 hwb6 32 128 2.0 42 140 pprm1 33

45
**Results with shannon Lattice**

Benchmark #Inputs #Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice 2to5 5 31 107 41 117 rd32 3 4 8 rd53 11 39 18 46 3_17 10 21 15 26 6sym 34 150 51 167 5mod5 14 58 30 81 4mod5 6 12 24 Ham3 7 xor5 Xnor5 Decod24 20 40 Cycle10_2 180 860 270 950 Ham7 22 32 68

46
**Results with shannon Lattice (cont..)**

Benchmark #Inputs #Gates pDv Lattice Cost pDv Lattice #Gates Shannon Lattice Cost Shannon Lattice Graycode6 6 5 Graycode10 10 9 Graycode20 20 19 nth_prime3_inc 3 4 8 nth_prime4_inc 16 48 29 61 nth_prime5_inc 91 39 101 Alu 17 22 4_49 52 58 Hwb4 12 28 15 31 Hwb5 24 96 38 110 Hwb6 32 128 40 134 Pprm1 33 14

49
Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account.

50
**Nearest Linear Node Model**

All gates are realized only on neighbors, but we have to add many SWAP gates Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM.

51
**Example of Positive Davio Lattice from [Perkowski97d]**

Example of Positive Davio Lattice from [Perkowski97d]. Positive Davio Expansion is applied in each node. Variable d is repeated

52
Transformation of function F3(a,b,c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates.(a) intermediate form, (b) final Quantum Array.

53
**Intermediate Structure with Dipal Gate**

4/17/2017 Intermediate Structure with Dipal Gate

54
**Another Representation of Quantum Array with Dipal Gate**

4/17/2017 Another Representation of Quantum Array with Dipal Gate

55
**Layered Diagram using Dipal Gate**

4/17/2017 Layered Diagram using Dipal Gate General layout of the layered diagram Each box represents a gate from family of Dipal gate

56
**General Pattern of Circuit with Dipal Gate**

4/17/2017 General Pattern of Circuit with Dipal Gate

57
**Quantum cost based On 1d model**

Benchmark #Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD 2to5 31 107 61 197 15 155 rd32 4 8 20 6 14 rd53 11 39 44 138 16 75 72 273 3_17 10 21 33 12 18 6sym 34 150 56 216 62 78 236 5mod5 58 17 67 90 48 204 4mod5 30 5 13 Ham3 3 7 Xor5 Xnor5 decod24 42 Cycle10_2 180 860 306 1238 19 1198 199 1738 Ham7 22 112 23 81 79 249

58
**Quantum cost based On 1d model**

Benchmark #Gates Lattice Cost Lattice #Gates with SWAP insertion for Lattice Cost with SWAP gates for Lattice #Gates DMM Cost DMM #Gates with SWAP insertion for MMD Cost with SWAP gates for MMD Graycode6 5 Graycode10 9 Graycode20 19 Nth_prime3_inc 4 6 12 Nth_prime4_inc 16 48 20 60 58 18 76 Nth_prime5_inc 29 91 39 121 26 78 128 384 Alu 17 7 23 4_49 52 41 127 40 130 hwb4 28 15 63 129 hwb5 24 96 44 156 104 64 224 hwb6 32 72 248 42 140 144 446 pprm1 33

59
**GENERALIZED REGULARITIES FOR QUANTUM AND NANO-TECHNOLOGIES**

60
**Ion-Trap Layout Interaction between two ions Single ion**

4/17/2017 Ion-Trap Layout Interaction between two ions ( a ) ( b ) ( c ) Single ion Various regular structures are technically possible, single dimensional vector is the one that is most often discussed ( d )

61
**Examples of Expansions for regular structures**

62
**Non-symmetric functions require repeatition of input variables**

Variable b is repeated

63
**Symmetry Indices and regular structures for binary logic**

64
**Multi-Valued Reversible Logic Adder**

Example: Multi-Valued Reversible Logic Adder

65
**Multi-Valued Reversible Logic**

68
**Three dimensional realization of lattices for ternary logic: SUM**

69
**Three dimensional realization of lattices for ternary logic: CARRY**

71
**QUANTUM CIRCUITS AND QUANTUM ARRAYS FROM TRULY QUANTUM GATES**

72
**Binary Reversible Gates**

4/17/2017 Binary Reversible Gates Basic single qubit quantum gates

73
**The transformations of blocks of quantum gates to the pulses level.**

74
**Transformation of the circuit realized in Fig. 7 using Toffoli gate**

Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap.

75
**Lattice based FPGA in CLASSICAL LOGIC**

76
New type of FPGA in CMOS In classical CMOS logic one can design a regular array, such as a form of FPGA, which realizes Shannon, positive Davio and negative Davio inside one cell. Such array is highly testable We can try to design something similar in quantum and reversible logic circuits.

77
Design of SRFPGA cell 4/17/2017 Dipal completed his MS in December 2000 with thesis on “Method for Self-Repair of FPGAs”. I adapted concept of Lattices which were developed Dr. Perkowski and Dr. Jeske to design FPGA like regular structure in VLSI This cell can be mapped to Shannon, positive Davio, negative Davio and other logic gates.

78
**General idea of SRFPGA architecture**

4/17/2017 General idea of the SRFPGA architecture, each circle represents cell shown on the previous foil. Row and column decoders are for memory addressing The next foil shows actual physical design of the SRFPGA

79
4/17/2017 SRFPGA layout With I/O pins

80
**Faults observed during column test**

4/17/2017 1 Faults observed during column test C = 2. Test output Var1 var2 var3 var4 var5 var6 var7 var8 var9 var10 var11 var12 var13 var14 var15 var16 I n p u t e s v c o r 1 Faults observed during diagonal test D = 2 1 1 1 T e s t o u p 1 1 1 1 1 1 1 1 Total number of Faults N = C * D = 2 * 2 = 4. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Input test vector

81
**This approach can be extended to reversible and quantum logic cicuits.**

4/17/2017 Dipal developed a unique test that identifies any number of faulty cell in the FPGA Repair is based on redundancy-repair where identified faulty cells are replaced with unused good cell in the structure Later Dipal adapted concept of lattice and synthesis methodology for designing reversible logic circuits. His method of reversible circuit design resolves many issues that are not yet addressed by any other researchers This approach can be extended to reversible and quantum logic cicuits.

82
**CONCLUSIONS and possible projects**

83
Conclusions Experimental results proved that our algorithm produced better results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic. New gate family called Dipal gate Presented new synthesis method with layered diagrams. More accurate technology specific cost model for 1D qubit neighborhood architecture.

84
4/17/2017 CONCLUSIONS A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates. A new family of gates called Dipal Gates. New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic function. Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice to QA). Program to implement a variant of MMD algorithm.

85
**Possible Projects Generalize to ternary logic**

4/17/2017 Possible Projects Generalize to ternary logic Generalize to all Dipal Gate Family gates. Realization with low level pulses for NMR technology. Development of a concept of reversible/quantum FPGA similar to SRFPGA Extend Agrawal-Jha method for factorized circuits. Extend the methods to many-output circuits.

86
**What to remember? Use of PPRM in synthesis of reversible circuits.**

The main idea of Agrawal-Jha algorithm. How AJ algorithm can be improved? How this algorithm can be extended to Fredkin gates? Expansions Rules for Lattice Diagrams Creating Positive Davio Lattice Creating Negative Davio Lattice Creating Lattice for arbitrary function with a mixture of Davio and Shannon Expansions. Lattices for symmetric functions. Transforming Positive Davio Lattice to a quantum array (circuit) for single output functions.

87
What to remember? Transforming Positive Davio Lattice to a quantum array (circuit) for single output functions. Transforming Positive Davio Lattice to a quantum array (circuit) for multi-output functions. Dipal gate and Dipal gate family. Regular structures and their use in quantum computing. Regularity versus LNNM model. Multiple-valued Lattices for ternary logic. FPGA based on 3*3 lattices and can they be adapted to quantum and reversible circuits. Decomposition to pulses. Relation to quantum costs.

Similar presentations

© 2020 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google