1 Random Number Generator Dmitriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan April 19, 2006 LVS and Simulation Project Objective: Create a Cryptologically Secure Pseudo-Random Number Generator that will revolutionize chaos

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3 Status C implementation Architecture Behavioral Design and Simulation Gate-Level Design and Simulation Preliminary Floorplan Schematic Design and Simulation Revised Floorplan Layout  Simulations Adder SRAM Registers Register to Register Analysis  Clock skew analysis  Layout Optimizations

4 Design Decisions Prepare for Control Additionally Buffer the Y Bus Power Distribution Ring Fill Design with as many vertical ground and vdd lines as possible Buffer clock skew in our favour

5 Final Layout

6 Middle of the Layout

7 Poly Layer

8 Metal 1 & 2 Masks

9 Metal 3 & 4 Masks

10 Lower & Upper Masks

11 Critical Delay

12 Part Trans Count AreaDensity Prop Delay Schematic #s ExtractRC #s Power 500MHz Power 500 MHz Adders (4) 5,856 (1,464 ea.) 25,200 um2 (6,300um2 ea.) ns 1.56 ns 600 uW 620 uW 140 uW 148 uW SRAM (M&R) 17,736 (M=10,458 R=7,278) 51,000 um2 (M=35,000 R=16, (M=0.293 R=0.456) 735ps 845ps W: 510 uW W: 3.25 mW R: 190 uW R: 1.40 mW 270 uW 1.86 mW Registers (10) 6400 (640 ea.) 38,400um2 (3,840um2 ea.) ps 275 ps 530 uW 590 uW 130 uW 145 uW Total ,000 um ns 475 MHz mW Putting it All Together

13 Questions? Comments?