EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 2 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 3 Circuit Under Design

EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Its Layout View

EE141 © Digital Integrated Circuits 2nd Manufacturing 5 The Manufacturing Process For a great tour through the IC manufacturing process and its different steps, check

EE141 © Digital Integrated Circuits 2nd Manufacturing 6 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

EE141 © Digital Integrated Circuits 2nd Manufacturing 7 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

EE141 © Digital Integrated Circuits 2nd Manufacturing 8 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

EE141 © Digital Integrated Circuits 2nd Manufacturing 9 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

EE141 © Digital Integrated Circuits 2nd Manufacturing 10 CMOS Process Walk-Through SiO 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well and V Tp adjust implants n (f) After p-well and V Tn adjust implants p

EE141 © Digital Integrated Circuits 2nd Manufacturing 11 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

EE141 © Digital Integrated Circuits 2nd Manufacturing 12 CMOS Process Walk-Through

EE141 © Digital Integrated Circuits 2nd Manufacturing 13 Advanced Metallization

EE141 © Digital Integrated Circuits 2nd Manufacturing 14 Advanced Metallization

EE141 © Digital Integrated Circuits 2nd Manufacturing 15 Design Rules

EE141 © Digital Integrated Circuits 2nd Manufacturing 16 3D Perspective Polysilicon Aluminum

EE141 © Digital Integrated Circuits 2nd Manufacturing 17 Design Rules  Interface between designer and process engineer  Guidelines for constructing process masks  Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

EE141 © Digital Integrated Circuits 2nd Manufacturing 18 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

EE141 © Digital Integrated Circuits 2nd Manufacturing 19 Layers in 0.25  m CMOS process

EE141 © Digital Integrated Circuits 2nd Manufacturing 20 Intra-Layer Design Rules Metal2 4 3

EE141 © Digital Integrated Circuits 2nd Manufacturing 21 Transistor Layout

EE141 © Digital Integrated Circuits 2nd Manufacturing 22 Vias and Contacts

EE141 © Digital Integrated Circuits 2nd Manufacturing 23 Select Layer

EE141 © Digital Integrated Circuits 2nd Manufacturing 24 CMOS Inverter Layout

EE141 © Digital Integrated Circuits 2nd Manufacturing 25 Layout Editor

EE141 © Digital Integrated Circuits 2nd Manufacturing 26 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

EE141 © Digital Integrated Circuits 2nd Manufacturing 27 Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

EE141 © Digital Integrated Circuits 2nd Manufacturing 28 Packaging

EE141 © Digital Integrated Circuits 2nd Manufacturing 29 Packaging Requirements  Electrical: Low parasitics  Mechanical: Reliable and robust  Thermal: Efficient heat removal  Economical: Cheap

EE141 © Digital Integrated Circuits 2nd Manufacturing 30 Bonding Techniques

EE141 © Digital Integrated Circuits 2nd Manufacturing 31 Tape-Automated Bonding (TAB)

EE141 © Digital Integrated Circuits 2nd Manufacturing 32 Flip-Chip Bonding

EE141 © Digital Integrated Circuits 2nd Manufacturing 33 Package-to-Board Interconnect

EE141 © Digital Integrated Circuits 2nd Manufacturing 34 Package Types

EE141 © Digital Integrated Circuits 2nd Manufacturing 35 Package Parameters

EE141 © Digital Integrated Circuits 2nd Manufacturing 36 Multi-Chip Modules