Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 21: Where do you go from here? Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l Proj#2 Due in 1 week l Exam Review in 1 week l Proj#2 Advising next Tuesday (in our regular classroom) l Course Evaluations Due Sunday before Exam Week l Final Exam Thursday, April 30, 1-4pm 1021 EB2 (regular classroom)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Today’s Lecture l Where do you go from here?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 How Can I Use this Stuff? l You have learned » how to design complex digital systems in Verilog, including a 16-bit micro-controller with approximately 1500 gates. » how to map these systems into Field-Programmable Gate-Arrays (FPGAs) l When would you use these design techinques? When the use of a micro-processor is - is too slow - consumes too much power - is too expensive

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Integrated Circuits (ICs) l Digital ICs are at the heart of nearly every electronic device l It’s all fine and good to use ICs, but what if you want to design ICs? l There are many more courses to take, each focusing on different levels of abstraction

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Levels of Abstraction l Each level of abstraction hides more of the complexity of the lower levels. l You can design more and faster at the higher levels, but you are always dependent on having good models from the lower levels. l Where you go from here depends on the level at which you like to work and where the jobs are.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Levels used in ECE 406 l Register-Transfer Level (RTL) » What’s Abstracted: Gates » Design Tools: Synopsys Design Compiler, Verilog Simulators » Why we use this level: Needed to get a cycle- accurate understanding of system behavior. l Gate/Cell Level » What’s Abstracted: Transistors » Design Tools: Synopsys Design Compiler, Verilog Simulators » Why we use this level: Needed to understand system delays and power

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Transistor Level l What’s Abstracted: Wires l Design Tools: SPICE Simulators, Cadence Virtuoso l Why we use this level: Needed to design new gates, circuits w/o gate-level representation

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Layout Level l What’s Abstracted: Quantum Effects l Design Tools: SPICE Simulators, Cadence Virtuoso l Why we use this level: Needed to accurately predict parasitic reistance, capacitance, and inductance and to generate mask patterns.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Electronic System Level (ESL) l Also called “Transaction-Level” l What’s Abstracted: Ports (1 ESL port = RTL ports), Cycles, Values l Design Tools: SystemC, SoC Designer l Why we use this level: Needed to co-simulate hardware and software in a reasonable amount of time

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 NCSU Course Offerings / ,706, 721

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 ECE 463/521 l Advanced Microprocessor Systems Design » Focuses on the design of software processors » Typically a higher level of abstraction than ESL

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 NCSU Course Offerings / / ,706,

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 ECE 464/520 l Application-Specific Integrated Circuit (ASIC) Design » Like 406, but explores optimization » Focuses on ASICs, rather than FPGAs critical-path delay: 3.3 ns area: 0.1 mm 2 power: 60 μW

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 ECE 745 l ASIC Verification » Writing test-benches » Quantification of the coverage of possible faults » Constrained-randomness » Probably the largest number of job opportunities

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 NCSU Course Offerings / / ,706,

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 ECE 546 l Very-Large Scale Integrated (VLSI) Systems Design x V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V ResistiveSaturation V DS = V GS - V T » Introduction to transistor and layout levels of abstraction for digital circuits

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 New in 546: Sources of Variation source: Mentor Graphics source: K. T. Cheung, UCSB source: Bernstein, et al., IBMJR&D’06 1) Dopant Fluctuation 3) Wire Capacitance Variation 2) Lithography Effects

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 ECE 733 l Digital Electronics » Focuses on very high-speed digital circuits, such as off-chip I/O

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 NCSU Course Offerings / / ,706,

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 ECE 761 l Design Automation for VLSI » Using Automated Place & Route tools to create Layout from Cells » Writing new CAD tools to perform this task

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 NCSU Course Offerings / / ,706, / ,557

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 ECE 404, 432/538 l ECE 404 – Introduction to Solid-State Devices l ECE 442/538 – Integrated Circuit Technology & Fabrication

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 NCSU Course Offerings / / ,706, System Design442/ ,557

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 New System-Design Course l System-on-Chip (SoC) Design » Will teach the use of SystemC & ESL Design Tools » Engineering Online Course (not yet offered)