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Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction Spring 2009 W. Rhett Davis.

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Presentation on theme: "Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction Spring 2009 W. Rhett Davis."— Presentation transcript:

1 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 1: Introduction Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l Labs to Start in 2 Weeks l HW#1 Due in 12 Days

3 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Today’s Lecture l Introduction l Brief Review of ECE 212 l Syllabus

4 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 ECE 406: A course in “building stuff” l Specification: Build a piece of hardware to perform Sobel edge detection on a stream of video. How would you build it? *Images by Evan Halley, Michael Chestnut, & Justin Walon, Senior Design Proj. Fall 2007 p = ||G x || 2 + ||G y || 2

5 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Approaches l ECE 206/306 Approach (Software) » Microcontroller & memory on an evaluation board, assembly language or C code to implement behavior l ECE 212 Approach (Hardware) » Logic Gates (flip-flops, AND & OR gates, multiplexers), –using discrete chips, breadboard, & wires –using a Field Programmable Gate Array (FPGA) l Which approach is better?

6 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Comparison of Approaches l Cost » Manufacturing / Materials (Recurring) » Design (Non-Recurring) l Performance » Speed » Power

7 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Analysis of Software Performance l Sobel algorithm needs » 16 AND Operations » 17 Shift Operations » 15 ADD Operations » 2 Multiply Operations » 50 Total per pixel l For NTSC Video (30 frames/sec, 640x480 resolution) » 50 x 30 x 640 x 480 = 461 MOPS (Million Operations per second)

8 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Analysis of Software Performance l Evan programmed the algorithm in C#, getting one frame in 16 seconds, rather than 30 frames per second l We can assume, however, that if programmed in C or C++, that it would meet the requirement. HardwareAMD Athlon 64x2 CPU + 1 GB DDR2 SDRAM Cost$46.95 + $20 SpeedEnough (if programmed properly) Power~ 100 W

9 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Analysis of Hardware Performance l Evan, Michael, & Justin mapped this design on to an Altera DE2 board and met the timing requirement l Power was 1000X smaller! l If we were to design an ASIC (Application Specific Integrated Circuit), it would also be much faster, but cost changes (higher design cost, lower manufacturing cost) HardwareAMD Athlon 64x2 CPU + 1 GB DDR2 SDRAM Altera Cyclone II EP2C20 FPGA Cost~$65~$45 SpeedEnough Power~ 100 W~0.1 mW

10 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 What are you likely to design? l Digital Still Camera (DSC) l CD Player l Satellite TV/Radio Receiver l Digital Cable Set-Top Box l Cellular Telephone l Wireless LAN Cards l HDTV Receivers l Cable Modems / DSL Modems Kodak DSC

11 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Kodak DSC System Overview source: http://www/ti.comhttp://www/ti.com Blue is on-chip, white is off-chip built around a TMS320DSC25 chip from Texas Instruments

12 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Hardware vs. Software l When to use a Hardware approach instead of a Software approach? l New Hardware is generally created whenever a micro-processor can’t be found that’s fast enough for a given application » Higher resolution camera » Higher quality video » Faster data-rate modem » etc. l ECE 406 is a HARDWARE DESIGN CLASS » You’ll design an LC-3 Microcontroller before it’s over

13 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Review of ECE 212 l Specification: Design a piece of hardware to read in 4 bits and allow the user to select one bit for output. Block Diagram (Sketch) Schematic

14 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Parts of a Schematic l Ports / Terminals » interface to outside world » how many? l Nets » internal connections » how many? l Symbols » simple (or “abstract”) representation of hardware » how many? l Instances » An occurrence of a symbol » how many

15 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 What is a Digital System? It is a organized collection of digital elements which is designed to perform specified operations on a set of digital inputs and to generate a set of digital responses. A digital system can be as simple as a block of combinational logic or as complex as a microprocessor.

16 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 What is a Digital System? Structure of digital systems: “system” vs. “module” For small systems which can be conveniently designed monolithically the terms “system” and “module” may be used interchangeably. A digital system can be created as a monolithic structure. Complex systems often need to be partitioned into some number of subsystems -- “modules”

17 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 What is a Digital System? Single module system: module data in control data out control System

18 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 What is a Digital System? Multiple module system: module data in control data out control System module data in control

19 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Inside the TMS320DSC25 chip How do we go about designing this?

20 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Step 1: Describe the Hardware l One approach: Simply describe the whole system as a set of schematics. l Then send your description off to a semiconductor company to fabricate for you. l What problems arise with this approach? » Drawing schematics takes too much time » How do you know for certain that it will work?

21 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Step 2: Simulate the Behavior l Automatically generate a timing diagram / waveforms to verify the behavior In[0] In[1] In[2] In[3] clock Out[0] Out[1] Out[2] Out[3] Clock In Out F 1 A 5 x F2AA

22 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Role of Hardware Description Languages l Modern digital chip and system design centers on the use of Hardware Description Languages (HDL) to capture the design at the Register Transfer Level (RTL) » RTL specifies all registers (flip-flops) and the combinational logic between the flip-flops » Capturing the design in RTL is much faster than drawing a schematic, because you don’t need to specify each gate. » But how do we get the final hardware?

23 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Step 3: Synthesize the Hardware l Modern design depends heavily on the use of Computer-Aided Design tools: » To synthesize the RTL design into a schematic » To turn the schematic into a chip layout, FPGA mapping or board layout » To verify the original design, and verify that the more detailed designs are consistent with the original design l Good designers depend critically on their ability to operate effectively with the CAD tools » Just knowing how to design logic is not enough » Unfortunately, you must learn a lot of tools and learn how to deal with their complexity and bugs » Its important to form a good understanding of the tool’s methodology HDLs simplify Design Capture & Design Automation

24 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 Synthesis-based chip design l The chip is designed using synthesis tools » Used when time-to-market is the most important issue l Basic Steps: Write HDL Simulate Snythesize Place&Route Verify

25 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 IC Design Approaches l HDL and synthesis based design is used in both Application Specific Integrated Circuits (ASICs): D-flip-flop NOR gate Place and Route Tool

26 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 …IC Design Approaches l and Field Programmable Gate Arrays (FPGAs): Xilinx FPGA architecuture Configurable Logic Block (CLB):

27 Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 Summary l Explain the differences between the following terms: » Schematic vs. Block Diagram » Port vs. Net » Symbol vs. Instance » System vs. Module » HDL vs. RTL

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