1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 9: State Machines & Reset Behavior Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l Exam #1 Thursday l HW#4 Due in 9 days

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l How do you infer flip-flops for an always@(posedge clock) procedure with blocking or non-blocking assignments? l Is it better to use blocking or non-blocking assignments in an always@(posedge clock) procedure? Why? l What are the key elements of the “simplified coding stlye”? l What Verilog constructs do you use to describe » MUXes » Control logic » Datapath logic » Registers l What would happen if you assigned the “zero” signal inside the always@(posedge clock) block in the “sophisticated style” example?

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Exam Review l State Machine Design l Using Reset Signals

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 State Machine Design l This is a state- transition diagram l If you were asked to design a state- machine to implement this diagram, how would you do it?

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Generalized State Machines l “Mealy Machine” » Most general » outputs labeled on transitions

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Moore Machine l Less General l Output depends on current state only

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 State Machine Design l Step 1: Assign States l Step 2: Create the state- register l Step 3: Write a combinational procedure to implement the state- update logic and output logic reg [1:0] current_state, next_state; always@(posedge clock) current_state <= next_state; always@(in or current_state) case (current_state) 0: if (in) next_state <= 0; else next_state <= 1; 1: if (in) next_state <= 2; else next_state <= 0; 2: next_state <= 0; default: next_state <= 0; endcase

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Sophisticated Style State Machine l Could you implement the output logic with this same always@ block? reg [1:0] state; always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Today’s Lecture l Exam Review l State Machine Design l Using Reset Signals

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Reset Signals l At the start of the simulation, state has the value X l What will the next state be? l Will this be the case with synthesized hardware? reg [1:0] state; always@(posedge clock) case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 Rules for Reset Signals l Only the edges for the clock and reset should be in sensitivity list l Reset condition should be specified first l No condition should be made on the clock

13. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Types of Reset Signals l Asynchronous: Reset happens as soon as reset signal is asserted l Synchronous: Reset is synchronized to clock always@(posedge clock or posedge reset) if (reset) value <= 0; else value <= next_value; always@(posedge clock) if (reset) value <= 0; else value <= next_value; Active-high reset

14. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Active-Low Reset l How would you implement an active-low asynchronous reset? WARNING: Popular Exam Question!

15. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Resetting the State Machine l We generally prefer synchronous resets to asynchronous, so that we don’t have to worry about the relative timing of the two signals reg [1:0] state; always@(posedge clock) if (reset) state <= 0; else case (state) 0: if (in) state <= 0; else state <= 1; 1: if (in) state <= 2; else state <= 0; 2: state <= 0; default: state <= 0; endcase

16. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Summary l How do you implement a state-machine when given a state-transition diagram? l Why in general do you need a reset-signal for a module? l What is the difference between synchronous and asynchronous reset signals?