PolyMUMPs® Design Rules

Slides:



Advertisements
Similar presentations
Simplified Example of a LOCOS Fabrication Process
Advertisements

CMOS Process at a Glance
ksjp, 7/01 MEMS Design & Fab Foundry Services: MOSIS as a model MOSIS: MOS implementation service, ISI, UCB HP Stanford Startup X MIT users Mask.
EE143 –Ali JaveySlide 10-1 Section 10: Layout. EE143 –Ali Javey Layout Design Rules (1) Absolute-Value Design Rules * Use absolute distances (2) -based.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.
Introduction to CMOS VLSI Design Lecture 0: Introduction
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Cmpe222_04des_rules_ppt.ppt1 VLSI Digital Systems Design Process Enhancements and Design Rules.
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Sample Devices for NAIL Thermal Imaging and Nanowire Projects Design and Fabrication Mead Mišić Selim Ünlü.
CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 05: IC Manufacturing Mary Jane Irwin (
One Way Circuits Limited
SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.
Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
RF MEMS devices Prof. Dr. Wajiha Shah. OUTLINE  Use of RF MEMS devices in wireless and satellite communication system. 1. MEMS variable capacitor (tuning.
Generated by IntelliSuite CleanRoom Electrothermal Actuator
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
Module-3 (MOS designs,Stick Diagrams,Designrules)
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Click mouse or hit space bar to advance slides All slides property of Cronos, all rights reserved Silicon Substrate Add nitride.
Chapter 4 Overview of Wafer Fabrication
IC Process Integration
ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.
Fabrication Technology(1)
Introduction to Prototyping Using PolyMUMPs
Norhayati Soin 05 KEEE 4426 WEEK 12/1 3/13/2005 KEEE 4426 WEEK 12 CMOS FABRICATION PROCESS.
MIT Lincoln Laboratory NU Status-1 JAB 11/20/2015 Advanced Photodiode Development 7 April, 2000 James A. Burns ll.mit.edu.
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process Jan M. Rabaey Anantha Chandrakasan.
CMOS Fabrication nMOS pMOS.
IC Fabrication/Process
NMOS FABRICATION 1. Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the required p-impurities.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
1 Overview of Fabrication Processes of MOSFETs and Layout Design Rules.
Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.
Design and Implement a Electro thermal Compliant
CMOS VLSI Fabrication.
CMOS FABRICATION.
Trieste, 8-10 November 1999 CMOS technology1 Design rules The limitations of the patterning process give rise to a set of mask design guidelines called.
(Chapters 29 & 30; good to refresh 20 & 21, too)
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.
Patterning - Photolithography
CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 05: IC Manufacturing Mary Jane Irwin (
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Subject Name: Fundamentals Of CMOS VLSI Subject Code: 10EC56
Manufacturing Process I
Geometric Design Rules
Layout and fabrication of CMOS circuits
Chapter 1 & Chapter 3.
Design Rule EMT 251.
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Digital Integrated Circuits A Design Perspective
Electrical Rules Check
Add nitride Silicon Substrate.
Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si
Process flow part 2 Develop a basic-level process flow for creating a simple MEMS device State and explain the principles involved in attaining good mask.
Memscap - A publicly traded MEMS company
Manufacturing Process I
(2) Incorporation of IC Technology Example 18: Integration of Air-Gap-Capacitor Pressure Sensor and Digital readout (I) Structure It consists of a top.
Manufacturing Process I
Add nitride Silicon Substrate
CSE 87 Fall 2007 Chips and Chip Making
Presentation transcript:

PolyMUMPs® Design Rules Memscap - A publicly traded MEMS company 4/16/2017 PolyMUMPs® Design Rules Allen Cowen A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 MUMPs® Design Rules Mask Conventions Nomenclature Minimum Feature/Space Rules Level-Level Rules Poly0 Poly1 & Dimple Poly2 Level-Level Rules (Graphic Form) Helpful Hints A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Rule Nomenclature Enclose L2 by L1 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Rule Nomenclature L1 to L2 Spacing A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Rule Nomenclature L2 Cut-Inside L1 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Rule Nomenclature L2 Cut-Outside L1 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Mask Conventions A Case Study

Level Names and Design Rules Memscap - A publicly traded MEMS company 4/16/2017 Level Names and Design Rules /2.5 /2.5 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 POLY0 Rules A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 POLY1 Rules A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 POLY2 Rules A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.5 A: POLY0 space to ANCHOR1--4.0um The necessary separation between POLY0 and ANCHOR1 hole to ensure that POLY0 is not exposed. B: POLY0 enclose ANCHOR1--4.0 um. The distance necessary between the edge of POLY0 and an ANCHOR1 hole to ensure the hole does not extend beyond the edge of POLY0. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.6 C: POLY0 enclose POLY1--4.0 um The amount POLY0 must extend beyond POLY1 to ensure that POLY0 is an effective ground plane for POLY1 structures. G: POLY1 enclose ANCHOR1--4.0 um. The amount that POLY1 must extend beyond the edge of an ANCHOR1 hole to ensure complete coverage of the hole. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.7 D: POLY0 enclose POLY2--5.0um The amount POLY0 must extend beyond the edge of a POLY2 structure to ensure that POLY0 is an effective ground plane. J: POLY2 enclose ANCHOR2--5.0 um. The amount POLY2 must extend beyond an ANCHOR2 hole to ensure complete coverage of the hole. A Case Study

Proper Enclosure of Layers Memscap - A publicly traded MEMS company 4/16/2017 Proper Enclosure of Layers Poly2 Poly1 Poly0 Metal A Case Study

Violation of Enclosure Rules Memscap - A publicly traded MEMS company 4/16/2017 Violation of Enclosure Rules stringer stringer thinned or breached nitride A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Stringers Poly1 Poly2 P1 Stringer A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.8 E: POLY0 enclose ANCHOR2--5.0um The amount POLY0 must extend past the edge of an ANCHOR2 hole to ensure the hole is over POLY0. F: POLY0 space to ANCHOR2--5.0um The amount of space between an ANCHOR2 hole and POLY0 necessary to prevent subsequent shorting between POLY0 and POLY2. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.9 H: POLY1 enclose POLY1_POLY2_VIA-4.0um The distance between the POLY1_POLY2_VIA hole and the edge of POLY1 necessary to ensure the via hole is entirely over POLY1. L:POLY2 enclose POLY1_POLY2_VIA--4.0um The amount POLY2 must extend beyond the POLY1_POLY2_VIA hole to ensure complete coverage of the hole. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.10 J:POLY2 enclose ANCHOR2--5.0um The amount POLY2 must extend beyond an ANCHOR2 hole to ensure complete coverage of the hole. I:POLY2 space to POLY1--3.0um The space required between POLY1 and POLY2 structures to ensure that the features are separate (no overlap). A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.11 K: POLY1 space to ANCHOR2--3.0um The space between a POLY1 structure and an ANCHOR2 hole necessary to avoid subsequent POLY1-POLY 2 contact. H: POLY1 enclose POLY1_POLY2_VIA--4.0um The distance between the POLY1_POLY2_VIA hole and the edge of POLY1 necessary to ensure the via hole is entirely over POLY1. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.12 M: POLY2 enclose METAL--3.0um The distance between the edge of METAL and a POLY2 structure necessary to ensure the entire metal area is on POLY2. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.13 N: POLY1 enclose DIMPLE--4.0um The amount POLY1 must extend beyond the edge of DIMPLE to ensure the DIMPLE is completely covered by POLY1. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.14 P: POLY2 cut-in POLY1--5.0um The minimum amount POLY2 must extend over a POLY1 structure to ensure overlap. O: POLY1 enclose POLY2--4.0um The minimum distance from the edge of POLY1 to POLY2 necessary to ensure the POLY2 does not overlap the POLY1 edge. Q: POLY2 cut-out POLY1--4.0um The minimum distance POLY2 must extend beyond the POLY1 edge to ensure complete edge overlap. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.15 R: Etch hole separation in POLY1: 30um The maximum separation distance between POLY1 etch holes necessary to ensure subsequent release of POLY1 structures. S: Etch hole separation in POLY2: 30um The maximum separation distance between POLY2 etch holes necessary to ensure subsequent release of POLY2 structures. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Fig. 2.16 T: HOLE2 enclose HOLE1--2.0um The necessary border of HOLE2 around HOLE1 to ensure good release results. U; HOLEM enclose HOLE2--2.0um The necessary border of HOLEM around HOLE2 to ensure good release results. A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Stacked Poly nitride oxide poly1 poly2 resist A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 A Case Study

Micromotor fabricated using Poly1/Poly2 stack Memscap - A publicly traded MEMS company 4/16/2017 Micromotor fabricated using Poly1/Poly2 stack P1/P2 interface A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Stacked Poly Error Patterned Poly 1 Pooled PR Residual Poly 2 A Case Study

Breaching the Nitride Layer Memscap - A publicly traded MEMS company 4/16/2017 Breaching the Nitride Layer ANCHOR1 POLY1 P1_P2_VIA or ANCHOR2 A Case Study

Memscap - A publicly traded MEMS company 4/16/2017 Words of Advice When drawing a level in layout, ALWAYS draw (digitize) the feature that you want represented on the wafer If you want a poly 1 beam, draw a polygon Draw a poly zero polygon where you want a poly zero electrode If you want a hole, draw a solid polygon to represent the hole A poly 1 or poly 2 line A dimple A Case Study 44

ANCHOR1+ POLY1_POLY2_VIA vs. ANCHOR2 Memscap - A publicly traded MEMS company 4/16/2017 ANCHOR1+ POLY1_POLY2_VIA vs. ANCHOR2 One of the most common layout errors is the use of ANCHOR1 + POLY1_POLY2_VIA instead of ANCHOR2 ANCHOR1 + POLY1_POLY2_VIA not equal to ANCHOR2 ANCHOR1 removes the oxide and allows poly 1 to contact substrate. If POLY1 is not drawn over the hole, the polysilicon will be removed in the RIE etch and the substrate is exposed to the polysilicon etch. resulting in removal of the nitride layer or etching into the substrate. ANCHOR2 was created to allow connection of poly 2 with the substrate in one mask and etch step When ANCHOR2 is used, the substrate is protected by oxide during the polysilicon etch. There is also no misalignment between the hole in the first and second oxides. A Case Study 45

FAQ Document; Galvanic Attack http://www.memscap.com/memsrus/docs/polymumps.faq.v2.pdf Material Data and properties, stress and specific PolyMUMPs layer information Galvanic Attack Effect – large metal pads near Poly0 features leads to breakage and discoloration of poly0. Process specific questions Can I do this questions?