The clock 10/23/20081ECE Lecture

Clocking Issues Clock Skew Gating the clock Section 8.8 of text 10/23/20082ECE Lecture

Clock Skew A definition – The difference in the arrival time of the clock at different devices. What gives rise to clock skew? 10/23/20083ECE Lecture

Clock Skew parameters For proper operation – t ffpd(min) + t comb(min) – t hold – t skew(max) > 0 – Where – t ffpd(min) -the propagation delay of F/F clk->Q – t comb(min) –the time for the combinational logic of the F/F – T hold –the hold time of the F/F – t skew(max) –the clock skew. Note that it subtracts from the hold time margin 10/23/20084ECE Lecture

Best to buffer the clock Take input clock into buffers that have less load then the entire chip/circuit 10/23/2008ECE Lecture5

Gating the clock When some elements of the circuit need to be sensitive at times and ignore the clock at others A simple AND gate approach – Can produce glitches – Causes excessive skew 10/23/2008ECE Lecture6

Preferred gating the clock This is a method that addresses the disadvantages of a simple AND gate. 10/23/2008ECE Lecture7