Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.

Slides:



Advertisements
Similar presentations
Malaviya National Institute of Technology
Advertisements

Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Technology
I have seen this happen !. You have exceeded your storage allocation.
Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
CMOS Fabrication EMT 251.
ECE/ChE 4752: Microelectronics Processing Laboratory
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
Dilbert.
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Top Side Conductor vacuum deposition Aluminum sputter deposit in Argon plasma CVC 601-sputter deposition tool.
1 N/P-Channel MOSFET Fabrication By Assoc. Prof Dr. Uda Hashim School of Microelectronic Enginnering KUKUM FOX N-Well Arsenic Implant LDD As+ S/D Implant.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.
Sample Devices for NAIL Thermal Imaging and Nanowire Projects Design and Fabrication Mead Mišić Selim Ünlü.
ACTFEL Alternating Current Thin Film Electroluminescent Lamps.
SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.
The Deposition Process
ECE 424 – Introduction to VLSI Design Emre Yengel Department of Electrical and Communication Engineering Fall 2012.
Thin Film Deposition Prof. Dr. Ir. Djoko Hartanto MSc
Device Fabrication Example
By Brandan Shelley.  With photolithography you start with a silicon disk. The silicon disk or wafer is first cleaned of any particles or imperfections.
Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.
Solar Cell conductive grid and back contact
Lecture 4 Photolithography.
5x mixed with 25x Reduction 1.Draw mask, keeping 25x features within a 3mm square, within the traditional 14-15mm 5x die 2.When printing masks scale 25x.
Lithographic Processes
McGill Nanotools Microfabrication Processes
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Fabrication of Active Matrix (STEM) Detectors
Nano/Micro Electro-Mechanical Systems (N/MEMS) Osama O. Awadelkarim Jefferson Science Fellow and Science Advisor U. S. Department of State & Professor.
Dilbert. Next steps in the antenna fabrication process Create a dielectric surface. The antenna must sit on a dielectric or insulating surface,
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
II-Lithography Fall 2013 Prof. Marc Madou MSTB 120
DILBERT. Did research and learned about several communication devices – cellular phones, Bluetooth/Wi-Fi, and RFID Did research and learned.
Microcontact Printing
Top Down Manufacturing
LITHOGRAPHY IN THE TOP-DOWN PROCESS - NEW CONCEPTS
#4 (Oct. 22) Photolithgraphy -What is photolithgraphy? -Thin-film patterning using phtolithgraphy -Applications of photolithgraphy -Trends in minimum pattern.
ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
Substitute beer and pizza?. Basic Silicon Solar Cell as fabricated in Cameron With Schematic.
©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.
Lithography in the Top Down Method New Concepts Lithography In the Top-Down Process New Concepts Learning Objectives –To identify issues in current photolithography.
Solar Cells need a top side conductor to collect the current generated They also need a conductive film on the backside.
LITHOGRAPHY IN THE TOP-DOWN PROCESS - BASICS
Fab - Step 1 Take SOI Wafer Top view Side view Si substrate SiO2 – 2 um Si confidential.
Antenna Project in Cameron clean room Wafer preparation, conductor deposition, photolithography.
Definition History Fabrication process Advantages Disadvantages Applications.
Farooq Ahmad Shah Manufacturing of Microprocessor.
CMOS Fabrication EMT 251.
Solar Cells need a top side conductor to collect the current generated They also need a conductive film on the backside.
IC Manufactured Done by: Engineer Ahmad Haitham.
Wisconsin Center for Applied Microelectronics
Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask.
DILBERT.
Dilbert.
Photolithography PEOPLE Program.
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Lithography.
Lecture 4 Fundamentals of Multiscale Fabrication
Layout and fabrication of CMOS circuits
ASPERA Technology Forum 20/10/2011
VLSI System Design LEC3.1 CMOS FABRICATION REVIEW
Silicon Wafer cm (5’’- 8’’) mm
Memscap - A publicly traded MEMS company
LITHOGRAPHY Lithography is the process of imprinting a geometric pattern from a mask onto a thin layer of material called a resist which is a radiation.
Laboratory: A Typical Lithography Process
Photolithography.
CSE 87 Fall 2007 Chips and Chip Making
Presentation transcript:

Photolithography Photolithography is the transfer of patterns, circuits, device structures, etc. to a substrate or wafer using light and a mask or stencil to stop the light. Photolithography was used extensively in the progression of microelectronics. Today, because of the sizes involved in current computer microprocessor devices, other methods like direct patterning using electron beams are used. Photolithography is still used for dimensions down to about 0.5um. The wavelength of UV light is .35-.45 um.

Starting material is a 100mm (4 inch) wafer of silicon - shown in an edge view

Wafers are cleaned first

Silicon Dioxide (SiO2 ) is grown on the silicon creating a dielectric or insulating layer

High temperature tube furnace for the formation of silicon dioxide (SiO2)

A conductor metal (student choice) is vacuum deposited on to the wafer

CVC 601-sputter deposition Conductor vacuum deposition tools in the ECE Microelectronics Clean Room Cooke-thermal deposition CVC 601-sputter deposition CHA Mark 50 e-beam deposition Varian 3125 e-beam deposition

UV light sensitive material called photoresist is spin coated on to the conductor side of the wafer

Light sensitive material is stored in amber dropper bottles – Use 1813 Wafers are spin coated with Shipley 1813 UV sensitive photoresist spin coating produces a uniform coating Spin speed is set here Light sensitive material is stored in amber dropper bottles – Use 1813 A vacuum chuck holds the wafer

The antenna design, arrayed on a transparency sheet, is placed on top of the wafer. This transparency is called a photo mask. Production photo masks would be made on glass plates with high precision patterns.

The array of antenna will be cut to just larger than the wafer The antenna pattern, arrayed and printed on a transparency paper, is used as a mask The array of antenna will be cut to just larger than the wafer

Ultraviolet light is projected down on to the photoresist coated wafer

HTG mask aligner and UV light source The UV light source is a mercury vapor lamp at 436nm wavelength UV light with filter surrounding it Clear glass plates are used to make sure the transparency lays flat to the wafer Exposure time set on timer Wafer is held by vacuum, mask is placed on top and brought into contact with wafer

The wafer is developed, leaving photoresist where no UV light has penetrated the mask

Solitec automatic developer Vacuum switch Start switch

Conductors are etched using chemicals specific to the metal Gold, silver, nickel, and copper etch Chrome etch Aluminum etch

After etching, the antenna pattern, in the conductor of choice, will be left on the wafer

In the clean room Complete one wafer first Determine the number of complete antennas on the wafer. Partial antenna can not be counted. Record this number. It is needed for the cost analysis. Evaluate cost – cost analysis will be next lesson Redesign if appropriate

Homework Find Excel and PowerPoint programs on Mosaic Begin learning how to use both programs A cost analysis for your antenna design will be due shortly Your project presentation will be done on PowerPoint