8xADC AMC board Tomasz Klonowski Warsaw University of Technology PERG – ISE

Requirements 8xADC (100 MHz) + FPGA for data acquisition and processing Form factor: AMC.1 (with PCIExpress), single width ADC: bit, ~100 MHz sample rate, conversion time 7 maximum clocks FPGA: Virtex 5 with external memory (2-4 MB, 250 MHz) 2 EEPROMs for FPGA 2 different clocks (configurable) for ADC 1-4 and ADC 5-8 clock distribution stability better than 5 ps IPMI additional signals from rear 8x analog signal MHz through signal conditioning connected to ADC 6x clock up to 100 MHz, LVDS bus, jitter less than 5 ps 2 of them connected to FPGA and ADC (user can choose clock for ADCs) 4 clocks connected to FPGA, LVDS bus

Block Diagram inhib it Clocks 3-6 I2C Data 8x16 bits Clocks 1-2 Data 8 bits Data 8 bits Data enable Clock configuration bus Data 36 bits Interconnector AMC connector A+AMC connector B+ Power supply uC Atmega 128 PCI Express JTAG FPGA Virtex5 XC5VLX30T EEPROM XCF16P JTAG ADC 1-4 AD6645 ADC 5-8 AD6645 Buffers Data 8x16 bits Analog signals 1-8 Clock distribution AD9510 AD9513 Signal conditioning band-pass filters Hot -swap switch Board with analog and clock distribution components Board with digital and IPMI components QDR II SRAM 512K x 36 IDT71P74604

Functional ADC AD bit, 80 – 105 MSPS, conversion time 4 maximum clocks, FPGA - Virtex 5 XC5VLX30T QDR II SRAM IDT71P Mb, 250 MHz EEPROM XCF16P for FPGA – two configurations IPMI Clock distribution AD9510, AD9513 – configured by FPGA clock distribution stability better than 5 ps 2 different clocks for ADC 1-4 and ADC 5-8 clocks configured by FPGA Buffers – 74LCX574 – for latching data from converters

Interface 8x analog signal MHz through signal conditioning connected to ADC 6x clock up to 100 MHz, LVDS bus 2 of them connected to FPGA and ADC (user can choose clock for ADCs) 4 clocks connected to FPGA, LVDS bus IPMBus Data 8 bits bus

Stage of work All schematics are done Layouts are expected to be finished by the end of January The prototype board is expected to be started by the end of February Tests of the protoype board are expected to be done by the and of April

Thank You for Your attention