Improved Migration-Enhanced Epitaxy for Self-Aligned InGaAs Devices Electronic Materials Conference (EMC), Mark A. Wistey University of California, Santa Barbara Now at University of Notre Dame U. Singisetti, G. Burek, A. Baraskar, V. Jain, B. Thibault, A. Nelson, E. Arkun, C. Palmstrøm, J. Cagnon, S. Stemmer, A. Gossard, M. Rodwell University of California Santa Barbara P. McIntyre, B. Shin, E. Kim Stanford University S. Bank University of Texas Austin Y.-J. Lee Intel Funding: SRC

2 Wistey, EMC 2009 Outline: Channels for Future CMOS Motivation for Self-Aligned Regrowth Facets, Gaps, Arsenic Flux and MEE Si doping and MEE Scalable III-V MOSFETs The Shape of Things to Come

3 Wistey, EMC 2009 Motivation for Self-Aligned Regrowth 3D nanofabrication Qi Xinag, ECS 2004, AMD AlGaAs GaAs InGaAs GaAs AlGaAs GaAs Blanket layers ? Device properties – Heat transfer – Contacts – Current blocking Air gap VCSEL, Dave Buell thesis Buried het laser, C-W Hu JECS 2007 W.K. Liu et al., J. Crystal Growth v. 311, p (2009) Integration: III-V’s on Si Heteroepitaxy Selective area growth And III-V MOSFETs...

4 Wistey, EMC 2009 Motivation for Regrowth: Scalable III-V FETs Classic III-V FET (details vary): Channel Bottom Barrier InAlAs Barrier Top Barrier or Oxide Gate Low doping Gap SourceDrain Large Rc { Large Area Contacts { Advantages of III-V’s Disadvantages of III-V’s III-V FET with Self-Aligned Regrowth: Channel In(Ga)P Etch Stop Bottom Barrier High-k Gate n+ Regrowth High Velocity Channel Implant: straggle, short channel effects Small R access Small Rc Self-aligned High doping: cm -2 avoids source exhaustion 2D injection avoids source starvation Dopants active as-grown High mobility access regions High barrier Ultrathin 5nm doping layer }

5 Wistey, EMC 2009 Process Flow Prior to Regrowth Pattern gate metal Selective dry etches SiN x or SiO 2 sidewalls Encapsulate gate metals Controlled recess etch (optional) Slow facet planes Not needed for depletion-mode FETs Surface clean UV ozone, 1:10 HCl:water dip & rinse, UHV deox (hydrogen or thermal) Regrowth In(Ga)P etch stop InAlAs barrier InP substrate Metals high-k Channel SiO 2, SiN x Fabrication details: U. Singisetti, PSSC 2009 Rodwell IPRM 2008

6 Wistey, EMC 2009 MBE Regrowth: Bad at any Temperature? Low growth temperature (<400°C): – Smooth in far field – Gap near gate (“shadowing”) – No contact to channel (bad) Gate 200nm Gap Source-Drain Regrowth Source-Drain Regrowth SEMs: Uttam Singisetti Metals Channel SiO 2 high-k Gate Source-Drain Regrowth Source-Drain Regrowth Regrowth: 50nm InGaAs:Si, 5nm InAs:Si. Si=8E19/cm3, 20nm Mo, V/III=35, 0.5 µm/hr. High growth temperature (>490°C): –Selective/preferential epi on InGaAs –No gaps near gate –Rough far field –High resistance

7 Wistey, EMC 2009 Gap-free Regrowth by MEE Migration-Enhanced Epitaxy (MEE) conditions: °C (pyrometer) As flux constant ~ 1x10 -6 Torr: V/III~3, not interrupted. 0.5nm InGaAs:Si pulses (3.7 sec), sec As soak Original Interface InGaAs Regrowth SiO 2 dummy gate SEM: Greg Burek Smaller gapCrosshatching—relaxation? High Si activation (4x10 19 cm -3 ). SEM: Uttam Singisetti InGaAs Regrowth SEM Cross Section SiO 2 dummy gate SEM Side View Top of gate: amorphous InGaAs Wistey, MBE 2008 RHEED: 4x2 ==> 1x2 or 2x4 ==> 4x2 with each pulse. Quasi-selective growth

8 Wistey, EMC C 490C460C SiO2 dummy gate 540C No gaps, but faceting next to gates Gap High Temperature MEE: Smooth & No Gaps Smooth regrowth Note faceting: surface kinetics, not shadowing. In=9.7E-8, Ga=5.1E-8 Torr

Wistey EMC Shadowing and Facet Competition [111] [100] Fast surface diffusion = slow facet growth Slow diffusion = rapid facet growth Shen & Nishinaga, JCG 1995 [111] faster [100] faster Shen JCG 1995 says: Increased As favors [111] growth SiO 2 [111] [100] Slow diffusion = fast growth Fast surface diffusion = slow facet growth SiO 2 Good fill next to gate. But gap persists

Wistey EMC Gate Changes Local Kinetics [100] 2. Local enrichment of III/V ratio 4. Low-angle planes grow instead SiO 2 1. Excess In & Ga don’t stick to SiO2 Diffusion of Group III’s away from gate Solution: Override local enrichment of Group III’s 3. Increased surface mobility

11 Wistey, EMC 2009 Control of Facets by Arsenic Flux SiO 2 W Cr Increasing As flux SEM of single-wafer growth series varying As flux Original Interface InAlAs markers InGaAs InGaAs Experiment: Vary As flux InAlAs marker layers Find best fill near gate 0.5x x x x10 -6 Lowest arsenic flux → “rising tide fill” No gaps near gate or SiO 2 /SiNx Tunable facet competition

12 Wistey, EMC 2009 Scalable InGaAs MOSFETs InGaAs Channel, NID 10 nm InAlAs Setback, NID Semi-insulating InP Substrate 5 nm Al 2 O 3 50 nm W 300 nm SiO 2 Cap SiNx 5 nm InAlAs, Si=8x10 19 cm nm InAlAs buffer 50 nm Cr n ++ regrowth Mo n ++ regrowth 3 nm InGaP Etch Stop, NID Top view SEM Oblique view

13 Wistey, EMC 2009 Scalable InGaAs MOSFETs InGaAs Channel, NID 10 nm InAlAs Setback, NID Semi-insulating InP Substrate 5 nm Al 2 O 3 50 nm W 300 nm SiO 2 Cap SiNx 5 nm InAlAs, Si=8x10 19 cm nm InAlAs buffer 50 nm Cr n ++ regrowth Mo n ++ regrowth 3 nm InGaP Etch Stop, NID Conservative doping design: [Si] = 4x10 13 cm -2 Bulk n = 1x10 13 cm -2 >> Dit Large setback + high doping = Can’t turn off High R source > 350 Ω-µm

14 Technique Shutter Pattern (Arsenic always open) [Si] (cm -3 ) n (cm -3 ) µ (cm 2 V -1 s -1 ) Conventional MBE8x x Si during Group III MEE pulse 8x x Si during As soak8x x Double Si doping16x Wistey, EMC 2009 Silicon Doping in MEE Electron concentration nearly constant Si prefers Group III site even under As-poor conditions Increased mobility by MEE Ga Si Ga Si Ga Si Ga Si

15 Wistey, EMC 2009 Regrown InAs S/D FETs side of gate top of gate Mo S/D metal with N+ InAs underneath 4.7 nm Al 2 0 3, 5×10 12 cm -2 pulse doping In=9.7E-8, Ga=5.1E-8 Torr SEM: Uttam Singisetti Gallium-free = improved selectivity in regrowth InAs regrowth InAs native defects are donors. 1 Reduces surface depletion. Decreased As flux works for InAs too. 1 Bhargava et al, APL 1997

16 Wistey, EMC 2009 InAs Source-Drain Access Resistance* *Wistey et al, NAMBE nm Al 2 0 3, InAs S/D E-FET. TLMs corrected for metal resistance. Slide: Uttam Singisetti, DRC 2009 Total R on = 600 Ω-μm ➡ R s < 300 Ω−μm. g m << 1/R s ~ 3.3 mS/μm -- Not source-limited. ➡ InAs contacts no longer limit MOSFET performance.

17 Wistey, EMC 2009 The Shape of Things to Come Generalized Self-Aligned Regrowth Designs: Channel Back Barrier Substrate Top Barrier Gate n+ Regrowth Self-aligned regrowth can also be used for: GaN HEMTs (with Nidhi in Mishra group, EMC 2009) InGaAs HBTs and HEMTs Selective III-V on Si — remove gaps THz and high speed III-V electronics Back Barrier Substrate Top Barrier Gate Recessed Raised Channel

18 Wistey, EMC 2009 Conclusions Reducing As flux improves filling near gate Self-aligned regrowth: a roadmap for scalable III-V FETs – Provides III-V’s with a salicide equivalent – Can improve GaN and GaAs FETs too Silicon doping impervious to MEE technique InAs regrown contacts improve InGaAs MOSFETs... – Not limited by source 1 mA/µm – Comparable to other III-V FETs... but now scalable

19 Wistey, EMC 2009 Acknowledgements Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain... McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm SRC/GRC funding UCSB Nanofab: Brian Thibeault, NSF