1. III-V CMOS: Device Design & Process Flows rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax ESSDERC Workshop on Germanium and III-V MOS Technology, Sept. 19, 2008 M. Rodwell University of California, Santa Barbara C. Palmstrøm, E. Arkun, P. Simmonds University of Minnesota P. McIntyre, J. Harris, Stanford University M. V. Fischetti, C. Sachs University of Massachusetts Amherst M. Wistey, U. Singisetti, G. Burek, A. Gossard, S. Stemmer, R. Engel-Herbert, Y. Hwang, Y. Zheng, C. Van de Walle University of California Santa Barbara P. Asbeck, Y. Taur, A. Kummel, B. Yu, D. Wang, Y. Yuan, University of California San Diego SRC Nonclassical CMOS Research Center

2. Why Develop III-V MOSFETs ? If FETs cannot be further scaled, instead increase electron velocity: InGaAs→ lower m*→ higher velocity I d / W g = qn s v I d / Q transit = v / L g Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current ( need > 1000 cm 2 /V-s mobility)

3. We Must Increase Drive Current To Reduce Delay Suppose we reduce L g but keep T ox fixed ? C gs is reduced, but I d /  V remains constant. Problem: Fixed C parasitic ~  r  o ; about 1 fF/  m. We have not reduced C parasitic  V / I d Instead, proportionally reduce both L g and T ox : → I d /  V increases, C gs remains constant → C gs  V / I d & C parasitic  V / I d are both reduced But drive current is limited by: source contact resistance and access resistance minimum gate dielectric thickness (tunneling) minimum channel thickness (Eigenstate Energy) low density of states in channel Must increase drive current (per unit FET periphery) (Fin- & Multi-Channel FETs improve both g m / G ds and C gs / C parasitic )

4. Low Effective Mass Impairs Scaling, Limits Current Approaches L-valley if well is thinner than 3-5 nm. → Hard to scale below 22 nm L g. Well energy (n is the # of band minima) Low mass impairs vertical scaling: Low mass limits transconductance: c dos comparable to 1 nm EOT oxide. Low mass limits charge, hence current E f reaches E L at ~ 10 13 / cm 2 charge density ( 5 nm well) where

5. Drive Current in the Ballistic & Degenerate Limits Inclusive of non-parabolic band effects, which increase c dos, InGaAs & InP have near-optimum mass for 0.4-1.0 nm EOT gate dielectrics eot includes the electron wavefunction depth

6. Device Design Target ( 22 nm L g ) Device > 5 mA/  m at 700 mV overdrive 10 13 /cm 2 carrier concentration < 10 nA/  m when off Channel : 1000 cm 2 /V-s at 5 nm thickness, 10 13 /cm 2 Dielectric: EOT < 1 nm, 0.6 nm preferable D it < 5*10 11 / cm 2 / eV S/D access resistance: 2*10 13 /cm 2 carrier density, < 5 nm thick

7. Design: MOSFET with Source / Drain Regrowth no gate barrier under S/D contacts high-K gate barrier Overlap between gate and N+ source/drain SourceDrain Gate HEMTs: high S/D resistance, low gate barrier K Shinohara Implanted III-V MOSFETs: implants too deep, too lightly doped

8. Design: Densities, Resistivities, Thicknesses

9. Process Flow with MBE Source/Drain Regrowth Wistey et al 2008 MBE conference

10. Gate Stack: Multiple Layers & Selective Etches Key: stop etch before reaching dielectric, then gentle low-power etch to stop on dielectric Wistey et al 2008 MBE conference

11. Sidewalls must be narrow and low leakage Electrostatics: Need sidewalls 5x10 18 /cm 3 (Asbeck/Taur) Problem: Thick sidewalls require large lateral recess, makes regrowth more difficult. Thin sidewalls can have high leakage current Wistey et al 2008 MBE conference

12. recessed S/D Recess Etch & Regrowth: Inter-Relationships InGaAs/InP composite channel permits selective InGaAs wet-etch, stopping on InP regrowth initiated on InP (desirable ?) Raised S/D process: easier regrowth, needs thinner (5 nm) sidewall raised S/D

13. Contact & Regrowth Interface Resistance Singisetti, Wistey

14. TEM of Regrowth: InGaAs on InGaAs InGaAs n+ HRTEM Interface HAADF-STEM` 2 nm Interface InGaAs n+ regrowth Wistey et al 2008 MBE conference

15. 15 S/D Regrowth by Migration-Enhanced Epitaxy MBE growth is line-of-sight → gaps in regrowth near gate edges MEE provides surface migration during regrowth→ eliminates gaps Original Interface InGaAs Regrowth SiO 2 dummy gate SEM: Greg Burek No gaps Smooth surfaces. SEM: Uttam Singisetti InGaAs Regrowth SEM Cross Section SiO 2 dummy gate SEM Side View (Oblique) Top of gate High Si activation (4x10 19 cm -3 ). Quasi-selective: no growth on sidewalls Wistey et al 2008 MBE conference Side of gate

16. Images of Completed Device Wistey et al 2008 MBE conference

17. Results & Status Extremely low drive current due to gaps between regrowth and gate SEM shows ~ 200nm gap on source & drain. Gap region is depleted of carriers because of surface states We will soon build new devices with M.E.E. S/D regrowth Singisetti et al, 2008 ISCS

18. Other Processes We Are Trying S/D MBE regrowth process is hard: developing a true 22 nm process on a 200 k$/year budget but to prove drive current capability we need a true 22 nm device Two other processes being developed (reduce risk): gate-last process→ S/D by MBE; regrowth not required other processes with ultra shallow N+ S/D regions

19. InGaAs/InP Channel MOSFETs for VLSI Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm Devices cannot scale much below 22 nm Lg→ limits IC density Little CV/I benefit in gate lengths below 22 nm Lg Gate dielectrics, III-V growth on Si: also under intensive development Need device structure with very low access resistance radical re-work of device structure & process flow

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21. Scaling: Constant Aspect Ratio for Constant g m /G ds Keep L g / T ox constant as we reduce L g

22. Rough Projections From Simple Ballistic Theory ChannelEOTdrive currentintrinsic (700 mV overdrive) gate capacitance InGaAs1 nm6 mA/  m 0.2 fF/  m InGaAs1/2 nm8.5 mA/  m 0.25 fF/  m Si1 nm2.5-3.5 mA/  m 0.7 fF/  m Si1/2 nm5-7 mA/  m 1.4 fF/  m 22 nm gate length InGaAs has much less gate capacitance 1 nm EOT → InGaAs gives much more drive current 1/2 nm EOT → InGaAs & Si have similar drive current InGaAs channel→ no benefit for sub-22-nm gate lengths 0.5-1.0 fF/  m parasitic capacitances

23. We Must Increase Transconductance To Reduce Delay Suppose we reduce L g but keep T ox fixed ? C gs is reduced, but g m remains constant. Problem: Fixed C parasitic ~  r  o ; about 1 fF/  m. We have not reduced C parasitic / g m Instead, proportionally reduce both L g and T ox : → g m increases, C gs remains constant → C gs / g m & C parasitic / g m are both reduced But Transconductance is limited by: source contact resistance and access resistance difficulties in reducing gate dielectric thickness difficulties in reducing channel thickness (Eigenstate Energy) low density of states in channel Must increase transconductance