8086 Microprocessor minimuim /maximuim mode By: hitesh lad

8086 Pin Diagram

THE 8086 MEMORY BANK D15-D8D7-D0 CS BHE A0A1---A19 UPPER BANK LOWER BANK ODD EVEN

Minimum Mode:

8086 Minimum Mode S5: Status of IF S6: 0

8086 Minimum Mode S5: Status of IF S6: 0

Maximum Mode:

Bus Timing for Read Operation

Bus Timing for Write Operation

Basic System Timing

Memory Architecture

TIMING SEQUENCE  AN EXTERNAL CLOCK GENERATOR DEVICE IS CONNECTED TO 8086 TO PROVIDE CLOCK SIGNALS THROUGHOUT THE SYSTEM.  ONE CYCLE OF CLOCK IS CALLED A STATE OR T-STATE.  EACH BASIC OPERATION SUCH AS READING A MEMORY LOCATION OR WRITING TO A PORT REQUIRES SEVERAL STATES.THIS GROUP OF STATES IS CALLED A MACHINE CYCLE.  THE TOTAL TIME REQUIRED TO FETCH AND EXECUTE AN INSTRUCTION IS CALLED AN INSTRUCTION CYCLE. AN INSTRUCTION CYCLE CONSISTS OF ONE OR MORE MACHINE CYCLE.

BASIC SIGNAL FLOW ON 8086 BUSES BASICALLY THERE ARE TWO OPERATIONS TO SEE: 1.READ OPERATION 2. WRITE OPERATION WILL SEE WHAT IS GOING ON DURING THIS TWO CYCLES OF OPERATION.

Memory READ CYCLE  HERE WE WILL SEE THE ACTIVITIES CARRIED OUT ON 8086 BUSES AT VARIOUS TIME INSTANTS WHEN IT READS FROM A MEMORY LOCATION OR FROM A PORT.  HERE WE WILL ASSUME THAT THE 8086 IS OPERATED IN IS MINIMUM MODE.

CLK M/IO ALE ADDR/ DATA ADDR/ STATUS RD/INTA READY DT/R DEN T1T2T3TWTW T4 A15-A0 A19-A16 RESERVED FOR DATA VALID D15-D0 MEMORY ACCESS TIME

WRITE CYCLE  HERE WE WILL SEE THE ACTIVITIES CARRIED OUT ON 8086 BUS AT VARIOUS TIME INSTANTS WHEN IT WRITES TO A PORT OR A MEMORY LOCATION.  HERE WE WILL ASSUME THAT THE 8086 IS OPERATED IN IS MINIMUM MODE.

CLK M/IO ALE ADDR/ DATA ADDR/ STATUS READY DT/R DEN T1T2T3TWTW T4 A15-A0 A19-A16 DATA OUT (D15-D0) WR

i/o write timing diagram

CLK M/IO ALE ADDR/ DATA ADDR/ STATUS READY DT/R DEN T1T2T3TWTW T4 A15- A0 A19- A16 DATA OUT (D15-D0) WR

ADDRESSING 1. ADDRESSING MEMORY 2. ADDRESSING PORTS DECODER IS THE CIRCUITRY USED FOR ADDRESING. IT SERVES TWO PURPOSES:  TO ENABLE RAM,ROM OR PORT.  TO MAKE SURE THAT ONLY ONE DEVICE IS ENABLED AT A TIME.

A SYSTEM ROM DECODER  TO UNDERSTAND THE CONCEPT A GENERAL DIGITAL SYSTEM WITH 8 DATA LINES AND 16 ADDRESS LINES IS CONSIDERED. THE HARDWARE USED CONSIST 2732 ROM-8(EACH-4 KB) 74LS138 DECODER/DEMULTIPLEXER 16 ADDRESS LINES 8 DATA LINES

ROM ROM ROM LS138 G2AG2BG1 Y0 Y1 Y7 A12 A13 A14 A15RD+5V D0 D5 D6 D7 A0 A1 A2 A1 1 CSCS CSCS CSCS

ADDRESS DECODER WORKSHEET A15 & A14-A12 A11-A8A7-A4A3-A0HEX EQUI. ADDRESS ROM0 ST. END = =0 F F F ROM1 ST. END = =1 F F F ROM2 ST. END = =2 F F F ROM3 ST. END = =3 F F F ROM4 ST. END = =4 F F F ROM5 ST. END = =5 F F F ROM6 ST. END = =6 F F F ROM7 ST. END = =7 F F F

A SYSTEM RAM DECODER TO THE SAME SYSTEM WE WANT TO ADD 16KB RAM.SO ADDITIONAL HARDWARE WE REQUIRE: 2142 RAM-8(EACH 2KB) ONE MORE 74LS138 DECODER/DEMULTIPLEXER  SINCE WE HAVE EACH RAM OF 2KB(2048 BYTES),WE NEED 11 ADDRESS LINES TO ADDRESS EACH MEMORY LOCATION WITHIN A RAM.AS WE HAVE OCCUPIED ADDRESSES 0000 THROUGH 7FFF FOR ROM.WE MUST START RAM ADDRESSES AFTER 7FFF.  SO WE HAVE 5 MORE ADDRESS LINES.WHICH WE WILL USE TO PROVIDE ADDRESS DECODING.

RAM RAM RAM LS138 G2AG2BG1 Y0 Y1 Y7 A11 A12 A13 A14A15 D0 D5 D6 D7 A0 A1 A2 A1 0 CSCS CSCS CSCS GND

A SYSTEM PORT DECODER A SYSTEM PORT CAN BE ADDRESSED IN TWO WAYS : 1.USING MEMORY MAPPED I/O- HERE A PORT IS TREATED AS IF IT IS A MEMORY LOCATION.  IT USES MEMORY RELATED INSTRUCTIONS.  THE OPERATION IS FASTER. A MAXIMUM OF 1MB INPUT AND 1MB(2 20 ) OUTPUT DEVICES CAN BE ADDRESSED. IT USES MEM.READ AND MEM.WRITE CONTROL SIGNALS.  IT CONSUMES THE ADDRESS RANGE USED BY PROGRAM MEMORY.  DECODING IS COMPLEX.

2.USING DIREC I/O-HERE AN INPUT OR AN OUTPUT DEVICE IS TREATED AS A DISTINCT I/O DEVICE.  IT DOES NOT CONSUME PROGRAM MEMORY.  THE DECODING IS SIMPLE.  IT USES IN AND OUT INSTRUCTIONS. A MAXIMUM OF 64K BYTE TYPE INPUT AND OUTPUT DEVICES CAN BE ADDRESSED OR 32K WORD TYPE INPUT AND OUTPUT DEVICES CAN BE ADDRESSED. IT USES IORD AND IOWRT CONTROL SIGNALS.  OPERATION IS SLOWER.

I/O read timinig diagram

CLK M/IO ALE ADDR/ DATA ADDR/ STATUS RD/INTA READY DT/R DEN T1T2T3TWTW T4 A15- A0 A19- A16 RESERVED FOR DATA VALID D15- D0 MEMORY ACCESS TIME

G1 G2B G2A 74LS138 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A1 5 A1 4 A1 3 A1 2 CS (CHIP SELECT) SIGNAL FOR PORT DEVICES A5A4A3

8086 PHYSICAL MEMORY THE TOTAL MEMORY (1MB) OF 8086 IS ARRANGED IN TWO BANKS. AN ODD BANK AND AN EVEN BANK. BOTH THE BANKS HAVE EQUAL NO. OF LOCATIONS. THE ODD BANK CONTAINS ODD NUMBERED MEM. LOCATIONS.IT IS KNOWN AS UPPER BANK. THE EVEN BANK CONTAINS ONLY EVEN NUMBERED MEM. LOCATIONS.IT IS KNOWN AS LOWER BANK. THIS ARRANGE MENT IS DONE IN ORDER TO SPEED UP THE OPERATION. THE ARRANGEMENT AND THE SIGNAL FOLLOWED, EXPLAINS THE SAME.

THE 8086 MEMORY BANK D15-D8D7-D0 CS BHE A0A1---A19 UPPER BANK LOWER BANK ODD EVEN

ADDRESSING WITH 8086  PROBLEM: TWO 16K ROM AND TWO 32K RAM ARE REQUIRED TO BE INTERFACED WITH 8086 CPU.THE RAM ADDRESS MUST START AT 00000H.THE ROM ADDRESS RANGE MUST INCLUDE FFFF0H IN ITS RANGE.

ADDRESS MAP THE RAM ADDRESS STARTS AT 00000H. TOTAL RAM IS 2*32K. SO RAM ADDRESS RANGE IS FROM 00000H TO 0FFFFH.(FFFF- 0000)H=2 16 =64K. SINCE THE ROM ADDRESS MUST INCLUDE FFFF0H. WE TAKE LAST ADDRESS OF ROM AS FFFFFH. AS TOTAL SPACE FOR ROM IS 2*16K,THE FIRST ADDRESS FOR ROM IS F8000H. (FFFFF-F8000)H=2 15 =32K. ADDRESS LINES A1-A14 ARE CONNECTED TO ROM.ADDRESS LINES A1-A15 ARE CONNECTED TO RAM.AND REMAINING LINES ARE USED FOR CHIP SELECTION.(NOTE: A0 IS RESERVED FOR BANKS.)

TO GENERATE THE CHIP SELECT SIGNAL THE FOLLOWING LOGIC IS USED: THE CHIPSELECT SIGNAL IS ACTIVE LOW. SO A PARTICULAR CHIP CAN BE SELECTED ONLY WHEN THIS SIGNAL IS LOW. SECONDLY AT A TIME ONLY ONE CHIP SHOULD BE SELECTED. FURTHER,THE ODD BANK WILL BE ENABLED ONLY IF BHE SIGNAL IS ACTIVATED.AND THE EVEN BANK WILL BE ENABLED ONLY IF AO SIGNAL IS LOW.

HERE WE CONSIDER AS AN EXAMPLE A SYSTEM WITH FEW PORTS. AN 8251(UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER) TWO 8255A(PROGRAMMABLE PARALLEL PORTS.) AN 8279 (DISPLAY AND KEYBOARD INTERFACING.) AN 8275 (CRT CONTROLLER) AN 8272A(FLOPPY DISK CONTRLLER)

74LS138 A15 A5 G2A G2B BHE OFFBOARD A4 A3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y RESERVED FOR FUTURE USE. PORTSELECTPORTSELECT G A2

MAP FOR PORTS A15-A5A4A3A2A1A0EQUI HEX ADDRESS =F F E O =F F E =F F E 4 =F F E =F F E 8 =F F E B =F F E C =F F E F =F F F 0 =F F F =F F F 4 =F F F 7

 LINES A1 AND A0 ARE USED FOR SETTING INTERNAL REGISTERS OF THE ADDRESSED PORT.  NOTE THAT THIS IS AN ABSOLUTE ADDRESSING.i.e. A PORT CAN BE SELECTED FOR ONLY ONE ADDRESS.  NON-ABSOLUTE ADDRESING ALSO EXISTS.THERE A PORT CAN BE SELECTED FOR MORE THAN ONE ADDRESSES.

THE OFF-BOARD DECODER  THE SDK-86 USES AN OFF-BOARD CIRCUITRY.  THE PURPOSE OF THIS CIRCUITRY IS TO PRODUCE AN ACTIVE LOW OFF BOARD SIGNAL WHENEVER THE 8086 ADDRESSES A PORT OR MEMORY WHICH IS NOT DECODED ON THE SDK-86 BOARD.  USUALLY WHEN WE CONNECT ADDITIONAL PORT USING DIRECT I/O, THIS DEVICE IS CONSIDERED AS OFF-BOARD(OUT OF THE DECODING MAP OF THE SYSTEM).  SO WHENEVER THIS PORT IS CALLED UPON,THE 8086 ASSERTS THE OFF BOARD SINAL.  TO COMMUNICATE WITH OFF BOARD DEVICES,EXTRA HARDWARE SUCH AS 74LS138 OR AN EPROM DECODER IS REQUIRED FOR ADDRESSING THIS DEVICE.

8088 MEMORY AND PORT ADDRESSING  IN 8088 THERE ARE ONLY 8 DATA LINES AND 20 ADD.LINES.  THE 8088 MEMORY IS NOT DEVIDED INTO ODD AND EVEN BANKS.BUT THERE IS ONLY A SINGLE BANK.  THERE ARE 1MB LOCATIONS EACH 1-BYTE LONG.SO TO READ OR WRITE A WORD 8088 REQUIRES TWO MACHINE CYCLES ALWAYS.

THE 8086 TIMING PARAMETERS  THE 8086 TIMING PARAMETERS ARE REQUIRED TO FIND WHETHER A PARTICULAR DEVICE IS FAST ENOUGH TO WORK IN OUR SYSTEM. IF NOT WE CAN USE WAIT STATES TO ALLOW THE SLOW DEVICE TO RESPOND.  THE 8086 RECEIVES TWO DIFFERENT CLOCK SIGNALS FRON 8284 CLOCK GENERATOR: 4.9MHz AND 2.45MHz USING A DIVIDE BY 2 NETWORK.

 NOW SUPPOSE THAT 8086 USES A FREQ. OF 4.9 MHz AND WE WANT TO DETERMINE WHETHER 2716 EPROMs ARE ABLE TO WORK CORRECTLY WITH OUR SYSTEM.  TO READ FROM EPROM, WE NEED TO PROVIDE ITS ADDRESS,WE ALSO NEED TO PROVIDE ITS CHIP SELECT SIGNAL AND IN ADDITION WE ALSO NEED TO ENABLE ITS OUTPUT.  FOR THIS,THE 8086 PROVIDES ON AD0-AD15 THE ADDRESS OF THE PARTICULAR LOCATION,THE CE (CHIP ENABLE-ACTIVE LOW) SIGNAL AND OE (OUTPUT ENABLE-AVTIVE LOW SIGNAL).

FROM A DATA BOOK THE TYPICAL ACCESS TIMES FOR EPROM 2716 ARE:  Tacc : 450 ns  THIS MEANS THAT IF 2716 HAS ITS CE AND OE SIGNALS ENABLED,THAN IT WILL TAKE AT THE MAX. 450 ns,AFTER THE ADDREES IS PUT ON AD0-AD15 LINES.  Tce: 450 ns  THIS MEANS THAT THE ADDRESS AND OE SIGNALS ARE ALREADY ENABLED THAN IT WILL TAKE AT THE MAX.,450 ns AFTER CE SIGNAL IS ENABLED.  Toe: 120 ns  THIS THE MAX. TIME REQUIRED WHEN AD0-AD15 AND CE SIGNALS ARE ENABLED BUT OUTPUT BUFFERS OF 2716 ARE NOT ENABLED.

NEXT, WE CHECK THAT EACH OF THESE TIMES ARE SHORT ENOUGH TO WORK WITH 8086 AT 4.9MHz.  LOOKING AT THE WAVE FORMS OF READ CYCLE THERE IS A TIME GAP BETWEEN THE STARTING OF STATE-T1 AND THE TIME AT WHICH VALID ADDRESS IS AVAILABLE.  THIS TIME INTERVAL IS SYMBOLISED AS TCLAV TIME FROM CLOCK LOW TO ADDRESS VALID. AS PER 8086 DATA SHEET THIS TIME IS 110 ns MAX.  AGAIN LOOKING AT READ CYCLE,WE FIND THAT VALID DATA MUST BE AVAILABLE BEFORE THE END OF T3.THERE ALSO EXISTS A TIME GAP BETWEEN,THE LINE IS AVAILABLE FOR PUTTING VALID DATA AND THE END OF STATE-T3.  THIS TIME INTERVAL IS SYMBOLISED AS TDVCL TIME DATA MUST BE VALID BEFORE CLOCK GOES LOW. AS PER 8086 DATA SHEET THIS TIME IS 30 ns.

 THE TIME BETWEEN THE END OF TCLAV AND THE START OF TDVCL IS THE TIME AVAILABLE FOR GETTING THE ADDRESS TO THE MEMORY AND TO Tacc THE MEMORY DEVICE.  THE TIME BETWEEN THE START OF TCLAV AND THE END OF TDVCL IS 3 T- STATES.  AT 4.9 MHz,TIME FOR ONE T-STATE IS 2.04 ns. SO TOTAL TIME FOR 3 STATES IS 612 ns.  FROM THIS WE SUBTRACT TCLAV AND TDVCL.  = =472 ns.

 SO, 472 ns AVAILABLE FOR CALLING 2716 AND ACCESSING ITS DATA.  NOW,LOOKING AT THE MINIMUM MODE SYSTEM,WE SEE THAT THE ADDRESS INFORMATION FOR 2716 GOES THROUGH LATCHES 74S373. SO, THE PROPOGATION DELAY FOR THIS MUST BE SUBTRACTED FROM 472 ns.THE PROPAGATION DELAY (CALLING TIME OR GETTING ADDRESS TO 2716 TIME) IS 12 ns. THIS LEAVES =460 ns AS Tacc.  SO FROM THIS WE SEE THAT THE Tacc NEEDED FOR 2716 IS 450 ns max. WHILE THE 8086 PROVIDES 460 ns, AT LEAST.  SO, WE CONCLUDE THAT WE DO NOT NEED ANY WAIT STATE TO BE INSERTED. AS FAR AS Tacc. IS CONCERN.

ANOTHER PARAMETER TOBE CHECKED IS Tce.  THE CE SIGNAL REQUIRES EITHER A0 OR BHE AS ITS ENABLE SIGNAL. SO,IT REQUIRES THE SAME CALCULATION AS THAT OF Tacc.  SO,Tce ALSO DOESN’T NEED WAIT STATE.  THE LAST TO BE SEEN IS Toe.  THE OE SIGNAL WILL BE GENERARED WHEN RD SIGNAL IS APPLIED.  NOW, LOOKING AT THE READ CYCLE RD SIGNAL WILL NOT BE ASSERTED TILL THE STATE T2.THE RD SIGNAL WILL BE ENABLED WITHIN A TIME TCLRL AFTER T2 STARTS.THE MAX. VALUE FOR THIS SIGNAL IS 165 ns. AGAIN,Toe MUST BE ACTIVE BEFORE VALID DATA IS PLACED ON AD0-AD15. i.e. BEFORE STARTING OF TDVCL.

 SO, SUM OF THESE TIMINGS MUST BE SUBTRACTED FROM THE TOTAL TIME AVAILABLE.  THE TOTAL TIME AVAILABLE IS STATE-T2 & T3.=408 ns.  =183 ns.  SO, 8086 PROVIDES 183 ns FOR ENABLING OUTPUT BUFERS.  WHILE THE TIME Toe REQUIRED BY 2716 IS 120 ns.  SO, FOR Toe ALSO WE NEED NO WAIT STATE.

TROUBLESHOOTING AN 8086 BASED MICROCOMPUTER  TROUBLESHOOTING IS TO FIND FAULTS IN A SYSTEM THAT WAS WORKING WELL, ONCE.  THE FOLLOWING STEPS ARE RECOMMENDED FOR A SYSTEMATIC AND TIME-EFFECTIVE TROUBLESHOOTING.

1.IDENTIFYING THE SYMPTOMS. CAREFULLY OBSERVE THE WORKING OF BAD SYSTEM AND TRY TO IDENTIFY THE SYMPTOMS. 2. MAKING A CAREFUL VISUAL AND TACTILE INSPECTION. CHECK FOR COMPONENTS THAT ARE EXCESSIVELY HOT. DO NOT TOUCH FIRMLY,BECAUSE IT MAY RESULT IN SKIN BURN. MAKE IT SURE THAT ALL ICs ARE FIRMLY SEATED IN THEIR SOCKETS AND NO PIN IS BENT. CHECK FOR BROCKEN WIRES AND LOOSE CONNECTORS.

3. CHECKING POWER SUPPLY. FROM THE MANUAL DETERMINE THE REQUIRED OPERATING VOLTAGE AND COMPARE IT WITH THE VOLTAGES AVAILABLE. ALSO CHECK THAT THE SAME VOLTAGE AVAILABLE AT PIN Vcc. 4. SIGNAL ROLL CALL. MAKE A CHECK AT SOME KEY SIGNALS e.g. CLOCK SIGNAL ON A CRO.OTHER SIGNAL SUCH AS ALE, RD AND WR SHOULD ALSO BE CHECKED.

5. SYSTEMATICALLY SUBSTITUTING ICs. THIS STEP CAN BE USED ONLY IF THERE ARE TWO IDENTICAL SYSTEMS. ONE IS WORKING AND THE OTHER IS NOT WORKING.AND ALSO ALL ICs ARE IN SOCKETS. FIRST TURN THE POWER OFF. MAKE MARKS ON THE ICs OF THE BAD SYSTEM.NOW EXCHANGE THE CPUs OF THE TWO SYSTEM AND SEE IF IT WORKS. IF SO, IT SURE THAT THE CPU IS BAD. IF NOT,RESTORE THE ORIGINAL CPUs.IN THIS WAY GO ON TESTING ICs. IF ROM IS ACCESIBLE AND RAM IS NOT,THEN TRY TO CHECK FOR RAM DECODER IC. THIS WAY YOU CAN LOCATE BAD IC/ICs.

6.TROUBLE SHOOTING A SYSTEM WITH SOLDERED-IN ICs. MOST OF THE TIME ALL ICs EXCEPT CPU AND ROM ICs ARE SOLDERED. TRY TO RUN THE BASIC MONITOR PROGRAM WHICH IS IN ROM,AND COMPARE THE SIGNALS ON THE TWO.THIS WILL PROBABLY LOCATE THE FAULTY IC. TRY TO EXCHANGE ROM OF THE TWO SYTEMS. AND/OR EXCHANGE CPU. THEN RUN A RAM TEST ROUTINE.THE ROUTINE WILL WRITE ALL 1’S TO SELECTED LOCATIONS.THEN, READ THIS DATA BACK IF THEY ARE NOT 1’S,THEN THE PROBLEM MAY BE WITH SYTEM BUS,(AS IT CAN NOY WRITE TO DESIRED LOCATION ) OR WITH RAM OR WITH RAM DECODER.

7.USING A LOGIC ANALYZER. A LOGIC ANALYZER SHOWS YOU SIGNALS ON 16 TO 64 LINES AT A TIME. IT GIVES YOU A SNAPSHOT OF LOGIC LEVELS WHICH ARE ON ITS INPUT LINES AT THE TIME OF TAKING SAMPLE OR “PHOTO”. SO, WE CAN CONNECT ALL THE DATA,ADDRESS AND CONTROL LINES TO THE INPUTS OF A LOGIC ANALYZER AND WE CAN SEE THE ACTIVITIES ON THIS LINES. THIS WILL SURELY TELL IF THE FAULT IS THERE WITH YOUR USING A LOGIC ANALYZER IS A VERY EFFECTIVE AND THE MOST SOPHISTICATED SYSTEM OF TROUBLE SHOOTING.BUT IT REQUIRES EXPERTISE IN USING THE ANALYZER.

8.OTHER EQUIPMENT. A LOGIC ANALYZER IS A BIG INSTRUMENT AND CAN NOT BE CARRIED WITH.TO USE THE SAME YOU ALSO NEED TO KNOW THE PROGRAMMING AND THE HARDWARE OF THE SYSTEM IN DETAIL. BUT SUPPOSE YOU ARE TO REPAIR SEVERAL DIFFERENT TYPES OF MICROPROCESSORS AND YOU DO NOT KNOW MUCH ABOUT THE PROGRAMMING OF THE SYSTEM WHICH YOU ARE TROUBLE SHOOTING,THEN YOU NEED TO USE EQUIPMENT SUCH AS FLUKE 9010A. SUCH EQUIPMENT KEEPS YOU FREE FROM THE STRESS OF KNOWING ALL THE SOFTWARE AND HARDWARE DETAILS OF THE SYSTEM AT HAND.