1. I/O Subsystem Organization and Interfacing Cs 147 Peter Nguyen
Chapter 4
I/O Subsystem Organization and Interfacing
Cs 147
Peter Nguyen

2. General Information Computer generally consists of three subsystems
Communication between subsystems by buses
The processors sends out the address to be accessed in memory or the address of the I/O device via the address bus
Data bus carries data between the subsystems
Information sent on the control bus coordinates all data transfers
The processor goes through an instruction cycle
Fetch an instruction from memory, and decode the instruction, and execute the instruction
All instructions are fetched and decoded in the same way, but the execute cycle is different for every instruction

3. Three Sections of the CPU
The register section, used for data storage
The arithmetic/logic unit, performs computations on data with the CPU
The control unit outputs signals to control the rest of the processor

4. Types of Memory Chips
ROM, PROM, EPROM, and EEPROM are all read only memory chips (data does not change)
SRAM and DRAM, these are random access memory (data change or lost when the computer is turned off)

5. Two types of I/O access Memory mapped I/O
Treats I/O device as if it were a memory location
The same instructions are used to access both memory and I/O devices, but memory and the I/O device cannot both use the same address
Isolated I/O
Different instructions are used to access I/O devices and memory
Requires an additional control line to distinguish between the two, but this allows memory and I/O devices to both use the same address

6. Presentation Outline : Part I
Input Module
Output Module
Bi-directional Module
An overall view within the organization of a simple computer

7. _________________________
-Definition -
_________________________

8. Memory is defined as homogeneous
From the CPU’s perspective, each location is read from and written to in exactly the same way

9. What’s the correlation ?
They are quite different but the comparisons is needed in order to understand the structure and organization of the computer

10. Memory vs. I/O Every memory has a unique address
Each memory location is read from and written to in exactly the same way, performs the same function – that is, its stores a data value or an instruction for use by the CPU
Every I/O device has a unique address
Perform vastly different functions; even though, they are part of the same subsystem

11. The major components of the Input Module
Input device (keyboard, mouse, …)
Tri-state buffers
Data bus
Enable logic (Address bus and Control Bus)

12. An input device: (a) with its interface and (b) the enable logic for the tri-state buffers

13. The tri-state buffers are used in input device interfaces to make sure that no more than one device writes data to the bus at any time.

14. Enable logic is the key to this design.
What is Enable Logic ?
Enable logic is the key to this design.
Because of the unique address, enable logic must not enable the buffers unless it receives the correct address from the address bus. It must also get the correct control signals from the control bus.

15. Components of the Output Module
Output device (monitor)
Register
Data bus
Enable Logic (Address bus and Control bus)

16. Output Device
The difference is in the REGISTER, the tri-state buffers are replaced by a register. Since the output devices read data from the bus, rather than write data, they do not need the buffers. The data is made available to all output devices; only the device with the correct address will read it in

17. ___
The output devices read data from the bus, rather that write data to it, they do not need the buffers. The data can be made available to all output devices; only the device with the correct address will read it in.

18. Load Logic
In the Output Module – the load logic plays the role of the enable logic in the input device interface. When this logic receives the correct address and control signals, it asserts the LD signal of the register, causing it to read data from the system’s data bus.

19. __
By doing so, the output device can then read the data from the register at its leisure while the CPU performs other tasks.

20. Components of the bi-directional module
I/O device (hard disk drive)
Two interfaces (one input, tri-state and one output, register)
Logic elements (gates to check address on the address bus)

21. Bi-directional module

22. I/O devices are much slower than CPUs and memory
Timing problems exist when interacting with the CPU

23. How does the CPU work around this processes ?

24. Ready
Normal inputs are high … when the CPU outputs the address of the I/O device and the correct control signals, enabling the tri-state buffers of the I/O device interface, the I/O device sets READY low.

25. … which cause the buffers to remain enabled.
The CPU reads this signal and continues to output the same address and control signals
… which cause the buffers to remain enabled.

26. By having the extra clock cycles generated when READY is set low
This is called wait states

27. Ready is good for small processes
Many systems actually use the interrupts

28. For larger computers
Interrupts
Direct memory access, DMA

29. Performs useful work while waiting for the much slower I/O devices
Interrupts
Performs useful work while waiting for the much slower I/O devices

30. Direct memory access (DMA)
… method used to bypass the CPU in the transferring process

31. Building a Simple Computer
CPU
8K of ROM, starting with address 0
8K of RAM
Memory mapped
Bidirectional I/O with a port address of 80000H
Read and Write control lines

32. Central Processing Unit (CPU)
16-bit addresses pin
Relatively
Simple
CPU
Systems data bus accesses
Read control lines
Write control lines

33. The memory subsystem Memory Subsystem 0000 0000 0000 0000
The memory configuration is 8K of ROM starting at address 0

34. To access the memory chip, the processor must supply an address used by the chip, as well as the proper control signals

35. Memory ROM RAM Address 001 Address 000 ROM chip will be enabled if 000
RAM chip will be enabled if 001
Address 001

36. Combinatorial logic is used to realize these functions and set the chip enable signals of the memory chips

37. ROM chip will output data only when its output enable and chip enable signals are asserted
RAM has two control inputs , RD and WR. Both the read and write signals from the control bus can drive these two signals

38. I/O subsystem
Register
Tri-state buffers
I/O Device

39. Freehand drawing of a computer organization
Address Bus
Memory
Subsystem
CPU
Data Bus
Control Bus
I/O Device
I/O Device
I/O Subsystem

40. Historical Perspective
Please see attached

41. Questions ?