1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2 Verilog Value Set 4 value logic system: 0represents low logic level or false condition 1represents high logic level or true condition Xrepresents unknown logic level Zrepresents high impedance logic level Note: x and z have limited use for synthesis

3 Four-valued Logic System Logical operators work on three-valued logic (0, 1, X) 01XZ XXX0XXXZ0XXX01XZ XXX0XXXZ0XXX Output 0 if one input is 0 Output X if both inputs are gibberish in1 in2 out in1 in2

4 The Power of Verilog: Integer Arithmetic Verilog’s built-in arithmetic makes a 32-bit adder easy: module add32 (a, b, sum) ; input [31:0] a, b ; output wire [31:0] sum ; assign sum = a + b ; endmodule A 32-bit adder with carry-in and carry-out: module add32_carry (a, b, cin, sum, cout) ; input [31:0] a, b ; input cin ; output wire [31:0] sum ; output wire cout ; assign {cout, sum} = a + b + cin ; // Concatenation endmodule

5 Quiz – Practice Practice writing the following numbers: 1. Decimal number 123 as a sized 8-bit number in binary. Use _ for readability. 8’b0111_ ’hX -4’d2 4’d14 ’h A 16-bit hexadecimal unknown number with all x’s. 4. An unsized hex number A 4-bit negative 2 in decimal. Write the 2’s complement for this number.

6 Quiz – Practice cont. Are the following legal strings? If not, write the correct strings. a. “this is a string ‘displaying the % sign” Not-legal, string must be contained on a single line Not-legal, includes \n = new line Legal b. “out = in1 + in2” c. “Please ring the bell \007” d. “This is a backslash \ character\n”

7 Quiz – Practice cont. Are these legal identifiers? Legal Not-legal, starts with a digit (number) Not-legal, starts with a $ sign a. system1 b. 1reg c. $latch d. exec$

8 Quiz – Practice cont. Declare the following variables in Verilog: a. An 8-bit vector net called a_in wire [7:0] a_in ; reg [31:0] address ; address = 32’d3 ; integer count ; b. A 32-bit storage register called address. Bit 31 must be the MSB (Little- Endian). c. Set the value of the register to a 32-bit decimal number equal to 3 d. An integer called count // integer = 32bits register

9 Quiz – Practice cont. e. A time variable called snap_shot // time = 64bits register integer delays[0:19] ; reg [63:0] MEM[0:255] ; parameter cache_size = 512 ; time snap_shot ; f. An-array called delays. Array contains 20 elements of the type integer g. A memory MEM containing 256 words of 64 bits each h. A parameter cache_size equal to 512 // a constant value declared within a module

10 CPU Address Bus Buffer Example module addr_buff(addr, abus, wr) ; input [31:0] addr ; input wr ; output [31:0] abus ; assign abus = (wr)? addr : 32’bZ ; endmodule module addr_buff_tb ; // test bench reg [31:0] addr ; reg wr ; wire [31:0] abus ; addr_buff UUT(addr, a_bus, wr) ; // UUT instantiation initial begin addr = 32’hAAAAAAAA ; wr = 0 ; #1 wr = 1 ; #1 addr = 32’h ; #1 wr = 0 ; #1 $finish ; end endmodule 3’S addr abus wr

11 CPU Address Bus Buffer Simulation Simulation results

12 CPU Data Bus Buffer Example module data_buff(dout, control, dbus) ; input [31:0] dout ; // write data input wr ; inout [31:0] dbus ; assign dbus = (control)? dout : 32’bZ ; endmodule module data_buff_tb ; // test bench reg [31:0] dout, Dbus ; // Dbus – data from external memory reg control ; wire [31:0] dbus ; data_buff UUT(dout, wr, dbus) ; // UUT instantiation initial begin dout = 32’hAAAAAAAA ; control = 0 ; Dbus = 32’h ; #1 control = 1 ; Dbus = 32’hZ ; #1 dout = 32’h ; #1 control = 0 ; Dbus = 32’h ; #1 $finish ; end endmodule 3’S dout dbus Read data wr

13 CPU Data Bus Buffer Simulation Simulation results