1. 1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System Workshop 5 - Data types A Workshop 6 - Data types B Workshop 7 - Operators Workshop 8 - Signed arithmetic Workshop 9 - Behavioral modeling A Workshop 10 - Behavioral modeling B Workshop 11 - Behavioral modeling C Workshop 12 - Data flow modeling Workshop 13 - Coding Styles

2. 2 Workshop 9 - Behavioral modeling A Structured Procedures - Initial, always Blocking and Non Blocking Procedural Assignments Assignment Styles for Sequential Logic Assignment Styles for Combinational Logic

3. 3 Structured Procedures – initial block There are two Basic Statements in Behavioral Modeling:  initial statement  always statement All other statements appear inside these statements. Verilog is concurrent language unlike C. All initial and always blocks run in parallel. All of them start at simulation time 0. Initial block starts at time 0 and executes only once. The initial statement provides a means of initiating input waveforms and initializing simulation variables before the actual description/simulation begins. Once the statements in the initial are exhausted, statement becomes inactive.

4. 4 initial blocks examples initial begin /* multiple statements, need to be grouped by begin-end */ clock=1’b0; nrst=1’b0; // clock & active low reset initial logic states end initial begin # 5 a = 1’b1 ; // set a to 1 @ simulation time 5 # 25 b = 1’b1 ; // set b to 1 @ simulation time 30 # 50 $finish ; // end simulation after 50 time ticks with system task end module Reg_File (port list) ; …….. // ports declaration reg [31:0] RegFile[0:31] ; // 32 x 32bit registers Register File integer i ; initial // Reset all Register File registers begin for(i = 0 ; i < 32 ; i = i + 1) // for loop RegFile[i] = 32’h0 ; end …….. // Register File read/write functionality endmodule

5. 5 Structured Procedures – always block A procedure that describes the function of a circuit. Can contain many statements like if, for, while, case always block starts at time 0 and executes statements continuously in a loop. always block waits for a change in a trigger signal and then the entire block (body) is executed at once. Statements in the always block are executed sequentially (= assignment) or in parallel (<= assignment). The final result describes the function of the circuit for current set of inputs. Intermediate assignments don’t matter, only final result. begin-end is used to group statements.

6. 6 always block examples // clock declaration, used mainly in Test Benches always #10 clock = ~clock ; // Toggle clock every half-cycle Combined Variable Declaration and Initialization - Variables can be initialized when they are declared: reg clock = 0 ; // Replaces reg clock ; initial clock = 0 ; Combined Port/Data Declaration and Initialization: output reg [7:0] sum = 0 ; output reg co = 0 ; Combined ANSI C Style Port Declaration and Initialization: module adder(output reg [7:0] sum = 0, output reg co = 0, input [7:0] a, b, input ci) ;

7. 7 and gate & full adder always block examples module and_gate (out, in1, in2) ; inputin1, in2 ; output reg out ; /*Implicit, not a real register! A Verilog register needed because of assignment in always block */ always @(in1 or in2) out = in1 & in2 ; endmodule ------------------------------------------------------------------------------------ module full_adder (sum, cout, a, b, cin) ; input a, b, cin ; output reg sum, cout ; // implicit register always @(a or b or cin) // Verilog 2001 allows (a, b, cin) {cout, sum} = a + b + cin ; // concatenation of cout & sum endmodule // If sensitivity list is too long, use (*), i.e. all inputs /*Specifies when block is executed i.e., triggered by which signals */

8. 8 “Complete” Assignments / Incomplete Triggers If an always block executes and a variable is not assigned: - Variable keeps its old value (think implicit state!) - NOT combinational logic  latch is inserted (implied memory) - This is usually not what you want: dangerous for the novice! Any variable assigned in an always block should be assigned for any (and every!) execution of the block Leaving out an input trigger usually results in a sequential circuit Example: The output of this “and” gate depends on the input history module and_gate (out, in1, in2) ; input in1, in2 ; output reg out ; always @(in1) // should be (in1 or in2) begin out = in1 & in2 ; end endmodule

9. 9 Procedural Assignments Update reg, integer, real or time variables values. Syntax :: = variable_lvalue = [delay or event control] expression can be one of the following: - A reg, integer, real, time, register variable or memory element - A bit select of these variables addr[0] - A part select of these variables addr[31:16] - A concatenation of any of the above {a[2:0], b[5:3]} reg_1 = 8’bAF ; integer_2 = -1 ; real_3 = 64’h0 ; time_4 = 64’b0 ;

10. 10 Blocking and Non Blocking Assignments Blocking assignment statements are executed in the order they are specified in a sequential block A blocking assignment will not block execution of statements that follows in a parallel block The = operator is used to specify blocking assignments Non-blocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block A <= operator is used to specify non-blocking assignments

11. 11 Blocking and Non-Blocking Assignments Examples reg [15:0] reg_a, reg_b; reg x, y, z; integer count; initial reg_a = 16’b0; begin// Blocking x = 0 ; y = 0; z = 0 ; count = 0 ; // Executed at time 0 reg_b = reg_a ;// Executed at time 0 #15 reg_a[2] = 1'b1 ; // Executed at time 15 #10 reg_b[15:13] = {x, y, z} ; // Executed at time 25 count = count + 1 ; // Executed at time 25 end begin // Non-Blocking x <= 0 ; y <= 0; z <= 0 ; count <= 0 ; // Executed at time 0 reg_b <= reg_a ; // Executed at time 0 #15 reg_a[2] <= 1'b1 ; // Executed at time 15 #10 reg_b[15:13] <= {x, y, z} ; // Executed at time 10 count <= count + 1 ; // Executed at time 0 end

12. 12 Non-Blocking Assignments Examples – cont. always @(posedge clock) /* read operation is performed on each right- end-side variable in1, in2, in3, reg1 @ positive edge of clock */ begin reg1 <= #1 in1 ; /* write operations to left-hand-side, are scheduled by delays or next clock negative edge*/ reg2 <= @(negedge clock) in2 ^ in3 ; reg3 <= #1 reg1 ; // The old value of reg1 end Race Conditions: // Two concurrent always blocks with blocking always @(posedge clock) a = b ; always @(posedge clock) b = a ; /* either a=b will be executed before b=a or vice versa The values of both registers will not be swapped */ Eliminate Race Conditions: /* Two concurrent always blocks with always @(posedge clock) non- blocking */ a <= b ; always @(posedge clock) b <= a ; // The values of both registers will be swapped

13. 13 Assignment Styles for Sequential Logic Blocking = Non-blocking <=

14. 14 Assignment Styles for Combinational Logic Blocking = Non-blocking <=

15. 15 Verilog Coding Guidelines When modeling sequential logic, use non-blocking assignments. When modeling latches, use non-blocking assignments. When modeling combinational logic with an always block, use blocking assignments. When modeling both sequential and combinational logic within the same always block, use non-blocking assignments. Do not mix blocking and non-blocking assignments in the same always block. Do not make assignments to the same variable from more than one always block. Do not make assignments using #0 delays.

16. 16 Exercise 1 – Counters Design a 4bit Up/Down Binary counter, employing synchronous reset. Write a Test Bench for the Up/Down Binary counter. Design a Decimal counter - counts from 0 to 9, employing asynchronous reset. Write a Test Bench for the Decimal counter.