Latches. Outline  Pulse-Triggered Latch  S-R Latch  Gated S-R Latch  Gated D Latch.

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Presentation transcript:

Latches

Outline  Pulse-Triggered Latch  S-R Latch  Gated S-R Latch  Gated D Latch

Outline  Pulse-Triggered Latch  S-R Latch  Gated S-R Latch  Gated D Latch

S-R Latch  Complementary outputs: Q and Q'.  When Q is HIGH, the latch is in SET state.  When Q is LOW, the latch is in RESET state.  For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW)  RESET state S=HIGH (and R=LOW)  SET state both inputs LOW  no change both inputs HIGH  Q and Q' both LOW (invalid)!

S-R Latch  For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH)  RESET state S'=LOW (and R'=HIGH)  SET state both inputs HIGH  no change both inputs LOW  Q and Q' both HIGH (invalid)!  Drawback of S-R latch: invalid condition exists and must be avoided.

S-R Latch  Characteristics table for active-high input S-R latch:  Characteristics table for active-low input S'-R' latch: SRSR QQ'QQ' SRSR QQ'QQ'

S-R Latch  Active-HIGH input S-R latch  Active-LOW input S’-R’ latch R S Q Q' S' R' Q Q' S' R' Q Q'

Outline  Pulse-Triggered Latch  S-R Latch  Gated S-R Latch  Gated D Latch

Gated S-R Latch  S-R latch + enable input (EN) and 2 NAND gates  gated S-R latch S R Q Q' EN S EN R Q Q'

Gated S-R Latch  Outputs change (if necessary) only when EN is HIGH.  Under what condition does the invalid state occur?  Characteristic table: EN=1 Q(t+1) = S + R'.Q S.R = 0

Outline  Pulse-Triggered Latch  S-R Latch  Gated S-R Latch  Gated D Latch

Gated D Latch  Make R input equal to S'  gated D latch  D latch eliminates the undesirable condition of invalid state in the S-R latch. D EN Q Q' D Q EN

Gated D Latch  When EN is HIGH,  D=HIGH  latch is SET  D=LOW  latch is RESET  Hence when EN is HIGH, Q ‘follows’ the D (data) input.  Characteristic table: When EN=1, Q(t+1) = D

Latch Circuits: Not Suitable  Latch circuits are not suitable in synchronous logic circuits.  When the enable signal is active, the excitation inputs are gated directly to the output Q. Thus, any change in the excitation input immediately causes a change in the latch output.  The problem is solved by using a special timing control signal called a clock to restrict the times at which the states of the memory elements may change.  This leads us to the edge-triggered memory elements called flip-flops.