1. Flip-Flops Basic concepts

2. A. Yaicharoen2 Flip-Flops A flip-flop is a bi-stable device: a circuit having 2 stable conditions (0 or 1) A flip-flop circuit has two outputs and the outputs of the flip- flop always complement each other, ie, both outputs remaining in “0” state or in “1” state. 3 Classes of Flip-Flops: Latches: outputs respond immediately while enabled (no timing control) Pulse-triggered flip-flops: outputs response to the triggering pulse Edge-triggered flip-flops: outputs responses to the control input edge

3. 3 Conventions The circuit is set means output = 1 The circuit is reset means output = 0 Flip-flops have two output Q and Q’ or (Q and Q) Due to time related characteristic of the flip- flop, Q and Q’ (or Q) are usually represented as followed: Q t or Q: present state Q t+1 or Q + : next state

4. 4 Clock Pulse: When the output of an electronic device goes from 0 to 1 state, remains in the 1 state for some time and comes back to 0 state, we get a pulse. The pulse may remain in high state for a fraction of a second or even for a few hours. The time for which the pulse remains in high state is called the “pulse width of the pulse”. The pulsed are produced and applied at regular intervals. They are called “Clock Pulses” or Clock(CLK)

5. 5 Memory Elements  Memory element with clock. Flip-flops are memory elements that change state on clock signals. Clock is square wave command Memory element stored value Q clock Positive edges Negative edges Positive pulses

6. 6 Memory Elements  The time interval between two pulses is called a period and denoted by T.  The reciprocal of T is called the frequency. ie, f = 1/T The frequency of clock means no. of clock pulses per second. The period is measured in seconds and the frequency is measured in Hertz.

7. 7 Memory Elements  Two types of triggering/activation:  pulse-triggered  edge-triggered  Pulse-triggered  latches  ON = 1, OFF = 0  Edge-triggered  flip-flops  positive edge-triggered (ON = from 0 to 1; OFF = other time)  negative edge-triggered (ON = from 1 to 0; OFF = other time)

8. 1/508 4 Types of Flip-Flops SR flip-flopJK flip-flop D flip-flopT flip-flop

9. S-R Latch9  Complementary outputs: Q and Q'.  When Q is HIGH, the latch is in SET state.  When Q is LOW, the latch is in RESET state.  For active-HIGH input S-R latch (also known as NOR gate latch), R=HIGH (and S=LOW)  RESET state S=HIGH (and R=LOW)  SET state both inputs LOW  no change both inputs HIGH  Q and Q' both LOW (invalid)!

10. S-R Latch10 S-R Latch  For active-LOW input S'-R' latch (also known as NAND gate latch), R'=LOW (and S'=HIGH)  RESET state S'=LOW (and R'=HIGH)  SET state both inputs HIGH  no change both inputs LOW  Q and Q' both HIGH (invalid)!

11. S-R Latch11 S-R Latch  Characteristics table for active-high input S-R latch :  Characteristics table for active-low input S'-R' latch: SRSR QQ'QQ' SRSR QQ'QQ'

12. S-R Latch12 S-R Latch  Active-HIGH input S-R latch  Active-LOW input S’-R’ latch R S Q Q'Q' S' R' Q Q'

13. 13 Gated SR latch (c)(c) Outputs change only when Enable(C) is HIGH.

14. A. Yaicharoen14 Master-Slave SR flip-flop