1. LECTURE IX CH 5 LATCHES AND FLIP-FLOPS

2. Sequential logic circuits by definition progressive from one logic state to the next. In order for this to occur, the circuit requires a means by which to temporarily remember where it is at any particular point in time so that inputs to the circuit can tell it which state to proceed to next. Single bit memory devices which perform this function are called latches and flip-flops. The most basic form of these is known as the SR latch. The S input (which stands for Set causes the Q output to go HI and 'Q to go LO. The R input (which stands for Reset) causes theQ output Q to LO and 'Q to go HI. These latches can be made from either NAND gates or NOR gates. Note that the NOR type requires a HI to activate S or R while the NAND type requires a LO. Activating both S&R at the same time will result in an unknown output state and is not allowed. The problem arises as the inputs are removed. Eventually, i.e. after the propagation delays within the circuit have concluded, a stable state will appear but its value cannot be predicted. This is known as a race condition. Once the outputs have been established, they will remain in that state until the device's inputs are once again activated.

4. D latches are designed to eliminate the possibility of activating both the S and R inputs simultaneously and ending up with an unknown result. This is accomplished by designing the latch with only one input called D which stands for Data. As can be seen from the diagram below, D is sent directly into one of the enabling NAND gates and inverted into the other one. Thus, the "S & R" inputs can never be the same. This type of D latch is said to be "transparent" because Q will follow D whenever EN is active.

6. Changing states in sequential logic circuits relies upon not only external inputs to the circuit but feedback from the memory devices used to define the current logic state itself. If transparent latches are used (i.e. ones who's outputs change whenever the enable is active) the resulting state may be indeterminate. The solution to this problem is to employ "edge-triggered" devices. These memory devices, will change states only during the transition of a HI to LO or from a LO to HI of the 'enable' input, which is now called a "Clock" input. One such device is the 74LS74 shown below.

7. Note that the '74 has a D input, both Q and 'Q outputs, and a CLK input which we have previously discussed, but also has a PRE (preset) and CLR (clear) inputs as well. These two inputs are said to be asynchronous because if they are activated they will immediately cause a change in the outputs regardless of the CLK input. The clock input (pin 3) is shown as an inward pointing triangle. This symbol indicates that the CLK will trigger on the leading (positive going) edge of the clock signal. If there were a circle just to the left of the triangle, this symbol would indicate that the CLK would trigger on the trailing (negative going) edge of the clock signal.

8. Show here are portions of the Texas Instruments Data Sheets for the 74LS74: