Pass Transistor Logic. Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated.

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Presentation transcript:

Pass Transistor Logic

Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated Electronics  Static CMOS Logic Circuits  Pseudo nMOS Logic Circuits  Pass Transistor Logic Circuits  Dynamic Logic Circuits  Case Studies

Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

nMOS Pass Transistor – Logic ‘1’ Transfer

nMOS Pass Transistor – Logic ‘0’ Transfer

PASS TRANSISTORS IN SERIES

PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

TRANSMISSION GATES  NMOS pass transistor passes a strong 0 and a weak 1.  PMOS pass transistor passes a strong 1 and a weak 0.  Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

TRANSMISSION GATE

PROBLEMS WITH TRANSMISSION GATES  No isolation between the input and output.  Output progressively deteriorates as it passes through various stages. However designs get simplified.

TRANSMISSION GATE - LAYOUT

PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

Multiplexor

Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

XOR gate

PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

D – Latch

TIMING ISSUES

D LATCH

D - LATCH

D LATCH – ALTERNATE CIRCUIT TOPOLOGY

PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

Static Flip Flop 0 1 D 1 0 Q Clk Transparent when Clk=0Transparent when Clk=1 At Clk= 0  1, Q = D. Else Q is held.

D Flip Flop – Circuit Diagram

D Flip Flop - Operation

D Flip Flop - Waveforms

Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

Handling Clock Skew Clk-in Clk Clk'

Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

Pass Transistor Logic Families  Complementary Pass Transistor Logic Family  Dual Pass Transistor Logic Family  Swing Restored Pass Transistor Logic Family

Problems  Design 4 to 1 multiplexor using transmission-gates.  Implement an XOR gate using minimum number of transistors.  Implement a full adder using transmission gates.

Solution - 1 C'0C'0 C0C0 C1C1 C'1C'1 Y A0 A1 A2 A3

Solution - 2 C'0C'0 C0C0 C'1C'1 A0 A1 A2 A3 C1C1 Y

XOR Gate AB ABAB