EKT 124 / 3 DIGITAL ELEKTRONIC 1 CHAPTER 3 Counters (cont.)

Example: Design a counter with the irregular binary count sequence 1,2,5,7,1,…..as shown in the state diagram. Use J-K flip-flops. 1. State Diagram

2. Next-state table Present State Next State Q2 Q1 Q0 1

Transition Table for a J-K flip-flop Output Transitions Flip-flop Inputs QN QN+1 J K  X 1

3.K-Map

4.The Counter Circuit

Example: State diagram for a 3-bit up/down Gray code counter.

The 74HC163 4-bit synchronous binary counter The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

Timing example for a 74HC163.

The 74LS160 synchronous BCD decade counter The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

Timing example for a 74LS160.

UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

Timing Diagram

The 74HC190 up/down synchronous decade counter.

Timing example for a 74HC190.

J and K maps - The UP/DOWN control input, Y, is treated as a fourth variable.

Three-bit up/down Gray code counter