1. CSCE 211: Digital Logic Design Chin-Tser Huang huangct@cse.sc.edu University of South Carolina

2. Chapter 7: The Design of Sequential Systems

3. 11/20/20123 Step 1: Represent each of the inputs and output in binary. Step 1.5: If necessary, break the problem into smaller subproblems. Step 2: Formalize the design specification either in the form of a truth table or of an algebraic expression. Step 3: Simplify the description. Step 4: Implement the system with the available components, subject to the design objectives and constraints. Review: Design Process for Combinational Systems

4. 11/20/20124 Design Process for Sequential Systems Step 1: From a word description, determine what needs to be stored in memory, that is, what are the possible states. Step 2: If necessary, code the inputs and outputs in binary. Step 3: Derive a state table or state diagram to describe the behavior of the system. Step 4: Choose a state assignment, that is, code the states in binary. Step 5: Choose a flip flop type and derive the flip flop input maps or tables. Step 6: Produce the logic equation and draw a block diagram (as in the case of combinational systems).

5. 11/20/20125 Revisit Continuing Example 6 CE6. A system with one input x and one output z such that z = 1 iff x has been 1 for at least three consecutive clock times.

6. 11/20/20126 State Assignment of CE 6 We use assignment (a) in our discussion of CE6.

7. Design and Output Truth Table of CE6 11/20/20127

8. 8 K-map for Next State q 1 * = x q 2 + x q 1 q 2 * = x q 2 ´ + x q 1

9. 11/20/20129 K-map for Output z = q 1 q 2

10. 11/20/201210 Therefore, D 1 = x q 2 + x q 1 D 2 = x q´ 2 + x q 1 Design with D Flip Flops

11. 11/20/201211 Implementation using D Flip Flops

12. 11/20/201212 Design with JK Flip Flops

13. 11/20/201213 J 1 = xq 2 K 1 = x´ z = q 1 q 2 J 2 = x K 2 = x´ + q´ 1 Design with JK Flip Flops

14. 11/20/201214 T 1 = x´q 1 + xq´ 1 q 2 z = q 1 q 2 T 2 = x´q 2 + xq´ 2 + xq´ 1 q 2 Design with T Flip Flops

15. Synchronous Counter A synchronous counter is a device with no data input that goes through a fixed sequence of states on successive clocks The output is often just the state of the system, i.e., the contents of all of the flip flops So no output column is required in the state table 11/20/201215

16. Example: 4-bit Binary Counter 11/20/201216

17. Design with JK Flip Flops 11/20/201217

18. 11/20/201218 Another Example: Up/Down Counter A counter that can count up or down according to a control input Counts up when x=0 Counts down when x=1

19. 11/20/201219 J A = K A = 1 J B = K B = x´A + xA´ J C = K C = x´BA + xB´A´ Design with JK Flip Flops

20. 11/20/201220

21. Another Example: Decimal Counter A decimal counter goes through the sequence 0 1 2 3 4 5 6 7 8 9 0 1 … Can you develop the truth table and then K- maps for the next state of each bit? 11/20/201221