1 Voltage Translation Clamps ASIA MARKETING DEVELOPMENT Samuel Lin Standard Logic 2012/Q1.

Slides:



Advertisements
Similar presentations
FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Gate Design n Static complementary logic gate structures. n Switch logic. n Other.
Advertisements

Digital Components Introduction Gate Characteristics Logic Families
Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
Operational Amplifiers
Demultiplexers Module M6.4 Section 6.4. Demultiplexers YIN 1 x 4 DeMUX d0d1 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 d1d0 0 0 YIN YIN YIN
TTL (Transistor Transistor Logic).  Transistor Transistor logic or just TTL, logic gates are built around only transistors.  TTL was developed in 1965.
EET 252 Digital Systems II Professor Nick Reeder.
Khaled A. Al-Utaibi 8086 Bus Design Khaled A. Al-Utaibi
Digital Electronics Logic Families TTL and CMOS.
9/20/6Lecture 3 - Instruction Set - Al1 The Hardware Interface.
Logic Families and Their Characteristics
 Circuit building blocks that compare the strength of two signals (usually Volts) and provide an output signal when one is bigger than the other are.
Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.
Voltage Transfer Characteristic for TTL
CMPE 118 MECHATRONICS Digital I/O Transistors and Mosfets.
VLSI Design EE213 VLSI DesignStephen Daniels 2003 R Vss R Vo Inverter : basic requirement for producing a complete range of Logic circuits.
03/11/03Nate Lamie Power Drivers. 03/11/03Nate Lamie Background Used to provide interface between low-level logic and power loads.
Lecture #24 Gates to circuits
© 2000 Prentice Hall Inc. Figure 6.1 AND operation.
Introduction to Op Amps
Digital I/O Connecting to the Outside World
ECE 447 Fall 2009 Lecture 6: TI MSP430 IO Interfacing.
In a not gate, if the input is on(1) the output is off (0) and vice versa.
CSET 4650 Field Programmable Logic Devices
Math – Getting Information from the Graph of a Function 1.
2005 MAPLD, Paper 240 JJ Wang 1 Total Ionizing Dose Effect on Programmable Input Configurations J. J. Wang, R. Chan, G. Kuganesan, N. Charest, B. Cronquist.
Electrical Characteristics of Logic Gates Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.
Interfacing Pressure Sensor to logic device input pin Click within the blue frame to access the control panel. Only use the control panel (at the bottom.
Spartan-II Memory Controller For QDR SRAMs Lobby Pitch February 2000 ®
IC Logic Families Wen-Hung Liao, Ph.D.
Renesas Electronics Europe GmbH A © 2010 Renesas Electronics Corporation. All rights reserved. RL78 Port architecture.
Logic Gate Specifications Definitions. Currents and Voltages All currents are defined as positive when they flow into the terminal of a logical gate.
Automatic accident avoiding system PROJECT MEMBERS MUTHUKUMAR.K (05ME33) SAKTHIDHASAN.S (05ME39) SAKTHIVEL.N (05ME40) VINOTH.S (05ME56) PROJECT GUIDE:
Bi-CMOS Prakash B.
SAMPLE AND HOLD CIRCUIT. CIRCUIT CONSTRUCTION The circuit samples the input and holds the last sample until the input sampled again. The circuit has an.
Unit 2 Logic Families.
Electrical Characteristics of ICs Part 3 Last Mod: January 2008  Paul R. Godin.
AND Gate Inputs Output Input A (Switch) Input B (Switch) Output Y (Lamp) 0 (Open) 0 (OFF) A B Lamp.
Electrical Characteristics of Logic Gates Gate Characteristics Last Mod: January 2008  Paul R. Godin.
Physical Properties of Logic Devices Technician Series Created Mar
2/June/2009LHCb Upgrade1 Single ended ADC Differential ADC –Convert single ended signal to differential (use AD8138 amp) –ASIC differential output ADC.
Digital-to-Analog Analog-to-Digital Week 10. Data Handling Systems  Both data about the physical world and control signals sent to interact with the.
Submitted by:.  Project overview  Block diagram  Power supply  Microcontroller  MAX232 & DB9 Connector  Relay  Relay driver  Software requirements.
Chapter 2. High-speed properties of logic gates.
LAPTOP THEFT IDENTIFIER.
Analog-Digital Conversion
For further information
Power amplifier circuits – Class AB
Logic Gates.
BRX Technical Training
Operational Amplifiers
0V 5V PWDN pin Pout 2V 50% TTL = 1.4V 90% Pout
Lesson 9: Digital Input-Output Signal Interfacing
Introduction to the OP AMP
Architectural Features
Digital Computer Electronics TTL
Lesson 5: Window Comparators
Lesson 3: op amp fundamentals and open loop applications
TTL Voltage Levels LOW HIGH Power Supply Range
Introduction to the OP AMP
Comparators with Hysteresis
Power amplifier circuits – Class AB
Data Distribution Board
Chapter – 2 Logic Families.
Auto-Bidirectional Translators
XC9500 Architectural Features
Low-Voltage PMOS-NMOS Bridge Drivers FAN3268 and FAN3278 Sales Fighting Guide With non-inverting and inverting logic channels, Fairchild Semiconductor’s.
FAN3268 and FAN3278 Low-Voltage Bridge Drivers
FPGA’s 9/22/08.
Logic Gates and Memory.
Presentation transcript:

1 Voltage Translation Clamps ASIA MARKETING DEVELOPMENT Samuel Lin Standard Logic 2012/Q1

Advantage With Voltage Clamp High Speed Translation Direction Control Unnecessary Low Ron for less distortion With 5V Supply, it can level shift 1V to 5V range on the Input/Outputs Bi-directional I2C™ Translation. GTL to TTL/LVTTL Translation Open Drain/Push Pull Interface 2

TVC Structures # k  B1A1 V REF A2 B2 VCC=5V A IO : non-open drain B IO : non-open drain V Pullup

TVC Structures # k  B1A1 V REF A2 B2 VCC=5V V Pullup A I/O : non-open drain B I/O : open drain

TVC Structures # k  B1A1 V REF A2 B2 VCC=5V A I/O : open drain B I/O : non-open drain V ref V Pullup

TVC Structures # k  B1A1 V REF A2 B2 VCC=5V V Pullup A I/O : open drain B I/O : open drain V ref

7 Flexible Bi-Direction

Typical Design Examples Passive Bi-Directional Translator Clamps. Pin “Gate” must use 200k  Pull Up to Vcc, which must be higher than VREF minimum 1V to turn on the FET. VREF would cut-off all A-Port Output to maximum level. A-Port has 5V input tolerant,need pull up when open drain B-Port is flexible to desired Logic Voltage Level which depends on pull up Vcc.

9 Up-Unique Direction

Example of Unique Up Translator k  B1A1 1.2V A2 B2 VCC=3.3V 3.3V CMOS LOGIC 200k  B1A1 1.2V A2 B2 VCC=3.3V 3.3V OPEN DRAIN 1.2V 1.2V Clamp to 3.3V

11 Down-Unique Direction

Example of Unique Down Translator k  B1A1 1.2V A2 B2 VCC=3.3V 3.3V CMOS LOGIC 200k  B1A1 1.2V A2 B2 VCC=3.3V 3.3V OPEN DRAIN 1.2V 3.3V Clamp to 1.2V