1. Renesas Electronics Europe GmbH 00000-A © 2010 Renesas Electronics Corporation. All rights reserved. RL78 Port architecture

2. © 2010 Renesas Electronics Corporation. All rights reserved. 2 Purpose This course provides an introduction to the RL78 port architecture. In detail these are the port hardware, control registers, driver capability and packages. Objective Learn about the RL78 port architecture. Understand the port capabilities. Content 19 slides (including this page) Learning Time 20 minutes Introduction

3. © 2010 Renesas Electronics Corporation. All rights reserved. 3 Special features for the RL78/G13 input/output ports Port function multiplexer to allow a flexible assignment of the peripherals –Multiplexing capability to relocate alternate functions to different pins Switchable input/output characteristics for dedicated I/O pins –CMOS or TTL –N-ch open drain EVDD allows to operate ports at different voltage than core –E.g core operated at 3V and ports operate at 5V 6V tolerance at 3V operation for dedicated port pins (n-ch open drain) –Interface to 5V peripheral when operating at 3V Ports

4. © 2010 Renesas Electronics Corporation. All rights reserved. 4 Port architecture

5. © 2010 Renesas Electronics Corporation. All rights reserved. 5 Pin I/O Circuit Types CMOS I port (2) –Schmitt-trigger behavior CMOS O ports (3-C) –Output only CMOS I/O port (5-AN) –Switchable between in- and output –Internal pull-up settable by software –Switchable CMOS or TTL input characteristic CMOS I/O port (13-R) –N-channel open drain –6V tolerant –Schmitt-trigger behavior in Input CMOS I port (37-E) –Oscillator Input pins –Input pins with Schmitt-trigger behavior Port structure

6. © 2010 Renesas Electronics Corporation. All rights reserved. 6 Pin I/O Circuit Types CMOS I/O port (11-x) –Switchable between A/D converter, logical input and output Port structure

7. © 2010 Renesas Electronics Corporation. All rights reserved. 7 Example for shared function Port mode control only for analogue pins No port mode control for digital shared pins Alternate function could be either: –wired-OR –wired-AND –or both Caution: Take care for the correct port settings. 0 Port architecture

8. © 2010 Renesas Electronics Corporation. All rights reserved. 8 Each port has its own set of flags. Port Latch Px.y Output data conntrol Input data read Port Mode register PMx.y Select the direction of a port Pull up control register Enable/ disable the internal pull-up Only in input mode Port Registers

9. © 2010 Renesas Electronics Corporation. All rights reserved. 9 Port Input Mode Control PIMx.y Select the Input Buffer Characteristics Normal Buffer VIH min = 0.8 EVDD TTL Buffer VIH min = 2.2V (@EVDD>4V) Port Output Mode Control POMx.y Select the Output Characteristics Port Mode Control Select between analog Input or digital I/O Only for analog ports Port registers

10. © 2010 Renesas Electronics Corporation. All rights reserved. 10 A/D port configuration ADPC Select between analog and digital input No independent setting (Analog starts at ANI0) Port Registers

11. © 2010 Renesas Electronics Corporation. All rights reserved. 11 Peripheral I/O direction register PIOR Used to multiplex I/O groups Advantages Use the available chip resources in an effective way and bring it to the I/O terminals To adapt the pin assignment to the most suitable PCB layout Timer0 I/O Analog I/O System I/O I2C_A0INTPn I2C_A0 INTPn PIOR Timer0 Analog I/O I2C_A0 INTPn System I/O PIOR Timer0 INTPn Timer0 I/O I2C_A0 Port Switching

12. © 2010 Renesas Electronics Corporation. All rights reserved. 12 Port drive capability

13. © 2010 Renesas Electronics Corporation. All rights reserved. 13 Port drive capability Maximum Port current drive Low –IOL = 20mA per pin –Total 170mA @70%duty High – IOH = 10mA per pin –Total 170mA @70%duty Allows: Direct LED drive No additional external components

14. © 2010 Renesas Electronics Corporation. All rights reserved. 14 P120/ANI19 P43 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 /RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS VDD EVDD 1 16 17 64 49 48 33 32 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4 P77/KR7/INTP11 P76/KR6/INTP10 P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06/TI06/TO06 P05/TI05/TO05 P30/INTP3/RTC1HZ/SCK11/SCL11 P147/ANI18 P146 P10/SCK00 P11/SI00/RXD0/TOOLRXD/SDA00 P12/SO00/TXD0/TOOLTXD P13/TXD2/SO20 P14/RXD2/SI20/SDA20 P15/SCK20/SCL20 P16/TI01/TO01/INTP5 P17/TI02/TO02 P55 P54 P53 P52 P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P00/TI00 P01/TO00 P02/ANI17/SO10/TXD1 P03/ANI16/SI10/RXD1/SDA10 P04/SCK10/SCL10 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 Sink: 15mA Source:10mA Sink: 20mA Total :100mA (Duty=70%) Source:10mA Sink: 20mA Total :70mA (Duty=70%) Total of All pins :170mA (Duty=70%) In case of 10 x 20mA LED drive 4 ports from line 6 ports from line A B A B Total current of line A = 80mA  70mA when duty=70% is the spec 80mA is possible when Duty=61.25% Total current of line B = 120mA  100mA when duty=70% is the spec 120mA is possible when Duty=40.8% Total current of pins are specified under condition of Duty=70%  To calculate Total current when Duty= n % Total output current = (Iout x 0.07)/(n x 0.01 ) * Iout = 70mA (Line-A) * Iout = 100mA (Line-B) Total current of pins are specified under condition of Duty=70%  To calculate Total current when Duty= n % Total output current = (Iout x 0.07)/(n x 0.01 ) * Iout = 70mA (Line-A) * Iout = 100mA (Line-B) Port drive capability Example of 64pin, VDD=4.0V~5.5V

15. © 2010 Renesas Electronics Corporation. All rights reserved. 15 Packages

16. © 2010 Renesas Electronics Corporation. All rights reserved. 16 Full pin compatibility over the whole pin range System pins 80 64 52 32 20 1 1 P2 P5 P1 P7 P0 Compatibility & Flexibility

17. © 2010 Renesas Electronics Corporation. All rights reserved. 17 7x7x1mm 0.4mm pitch 7x7x1.4mm 0.5mm pitch 6.5x8.1mm 0.65mm pitch 4 x 4 x 0.75mm 0.5mm pitch 5 x 5 x 0.75mm 0.5mm pitch 3 x 3 x 0.69mm 0.5mm pitch 4 x 4 x 0.69mm 0.4mm pitch 4 x 4 x 0.69mm 0.5mm pitch 25pin LGA36pin LGA64pin FBGA 24pin QFN32pin QFN40pin QFN 6 x 6 x 0.75mm 0.5mm pitch 48pin QFN 7 x 7 x 0.75mm 0.5mm pitch 20pin SSOP30pin SSOP 9.7x8.1mm 0.65mm pitch 48pin LQFP64pin TQFP 12x12x1mm 14x14x1mm 0.5mm pitch 80pin TQFP 14x14x1mm 14x20x1mm 0.5mm pitch 100pin TQFP 14x20x1mm 0.5mm pitch 128pin TQFP RL78 - Wide rang of packages Different packages for each customer request

18. © 2010 Renesas Electronics Corporation. All rights reserved. 18 Advantage of QFN Package Reduced PCB size eg. for sensor applications The mounting space for a 32-pin QFN devices is only about 30% of the space needed for its 30-pin SSOP equivalent. 32 pin 69% space savings 48 pin 40% space savings 40 pin 75% space savings 5x5 mm² 6x6 mm² 7x7 mm²

19. © 2010 Renesas Electronics Corporation. All rights reserved. 19 Topics Covered: The RL78 port architecture. Port Hardware Control Registers Driver Capability Available Packages For more information on the RL78 or other Renesas product offerings, please visit www.renesas.comwww.renesas.com Thanks for viewing! Summary

20. Renesas Electronics Europe © 2010 Renesas Electronics Corporation. All rights reserved. Thank You