Instructor: Yuzhuang Hu Final Exam! The final exam is scheduled on 7 th, August, Friday 7:00 pm – 10:00 pm.

Slides:

Advertisements

Similar presentations

Adding the Jump Instruction

Advertisements

Morgan Kaufmann Publishers The Processor

COMP25212 Further Pipeline Issues. Cray 1 COMP25212 Designed in 1976 Cost $8,800,000 8MB Main Memory Max performance 160 MFLOPS Weight 5.5 Tons Power.

Mehmet Can Vuran, Instructor University of Nebraska-Lincoln Acknowledgement: Overheads adapted from those provided by the authors of the textbook.

Pipeline Computer Organization II 1 Hazards Situations that prevent starting the next instruction in the next cycle Structural hazards – A required resource.

Lecture Objectives: 1)Define pipelining 2)Calculate the speedup achieved by pipelining for a given number of instructions. 3)Define how pipelining improves.

ELEN 468 Advanced Logic Design

Pipeline Hazards Pipeline hazards These are situations that inhibit that the next instruction can be processed in the next stage of the pipeline. This.

331 W08.1Spring :332:331 Computer Architecture and Assembly Language Spring 2006 Week 8: Datapath Design [Adapted from Dave Patterson’s UCB CS152.

Instructor: Yuzhuang Hu The Shifter 3 clock cycles will be needed if using a bidirectional shift register with parallel load.  A clock.

Pipelining II Andreas Klappenecker CPSC321 Computer Architecture.

ENEE350 Ankur Srivastava University of Maryland, College Park Based on Slides from Mary Jane Irwin ( )

©UCB CS 162 Computer Architecture Lecture 3: Pipelining Contd. Instructor: L.N. Bhuyan

1 COMP541 Sequencing – III (Sequencing a Computer) Montek Singh April 9, 2007.

L18 – Pipeline Issues 1 Comp 411 – Spring /03/08 CPU Pipelining Issues Finishing up Chapter 6 This pipe stuff makes my head hurt! What have you.

L17 – Pipeline Issues 1 Comp 411 – Fall /1308 CPU Pipelining Issues Finishing up Chapter 6 This pipe stuff makes my head hurt! What have you been.

The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture.

Lec 9: Pipelining Kavita Bala CS 3410, Fall 2008 Computer Science Cornell University.

Appendix A Pipelining: Basic and Intermediate Concepts

Computer ArchitectureFall 2008 © October 6th, 2008 Majd F. Sakr CS-447– Computer Architecture.

Computer Architecture - A Pipelined Datapath A Pipelined Datapath  Resisters are used to save data between stages. 1/14.

Instructor: Yuzhuang Hu Assembly Lines An assembly line is a manufacture process in which parts are added into a product in a sequential.

COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections

1 Pipelining Reconsider the data path we just did Each instruction takes from 3 to 5 clock cycles However, there are parts of hardware that are idle many.

Memory/Storage Architecture Lab Computer Architecture Pipelining Basics.

CS1104 – Computer Organization PART 2: Computer Architecture Lecture 12 Overview and Concluding Remarks.

Pipelined Datapath and Control

Instructor: Yuzhuang Hu Midterm The midterm is schedule on June 17 th, 17:30-19:30 pm. It covers the following:  VHDL Programming. 

Chapter 4 CSF 2009 The processor: Pipelining. Performance Issues Longest delay determines clock period – Critical path: load instruction – Instruction.

Comp Sci pipelining 1 Ch. 13 Pipelining. Comp Sci pipelining 2 Pipelining.

Instructor: Yuzhuang Hu Design strategy in ASM.

Pipeline Hazards. CS5513 Fall Pipeline Hazards Situations that prevent the next instructions in the instruction stream from executing during its.

Ch. 10 Central Processing Unit Designs - CISC. Two CPU designs CISC –Non-pipelined datapath with a micro- programmed control unit RISC –Pipelined datapath.

Elements of Datapath for the fetch and increment The first element we need: a memory unit to store the instructions of a program and supply instructions.

Lecture 15: Pipelined Datapath Soon Tee Teoh CS 147.

Lecture 9. MIPS Processor Design – Pipelined Processor Design #1 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System.

Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data.

COM181 Computer Hardware Lecture 6: The MIPs CPU.

MIPS processor continued. Review Different parts in the processor should be connected appropriately to be able to carry out the functions. Connections.

CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.

Pipelining: Implementation CPSC 252 Computer Organization Ellen Walker, Hiram College.

Computer Architecture Lecture 6.  Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions:

RISC Pipelining CS 147 Spring 2011 Kui Cheung

Computer Organization

Pipelining Chapter 6.

RISC Pipelining RISC Pipelining CS 147 Spring 2011 Kui Cheung.

CSCI206 - Computer Organization & Programming

Morgan Kaufmann Publishers

ELEN 468 Advanced Logic Design

Morgan Kaufmann Publishers The Processor

Morgan Kaufmann Publishers The Processor

CDA 3101 Spring 2016 Introduction to Computer Organization

Design of the Control Unit for Single-Cycle Instruction Execution

MIPS processor continued

Morgan Kaufmann Publishers The Processor

CSCI206 - Computer Organization & Programming

ELEC / Computer Architecture and Design Spring Pipelining (Chapter 6)

Pipelining Chapter 6.

Design of the Control Unit for One-cycle Instruction Execution

Systems Architecture II

CSCI206 - Computer Organization & Programming

Rocky K. C. Chang 6 November 2017

The Processor Lecture 3.2: Building a Datapath with Control

Data Dependence Distances

Instruction encoding We’ve already seen some important aspects of processor design. A datapath contains an ALU, registers and memory. Programmers and compilers.

Control units In the last lecture, we introduced the basic structure of a control unit, and translated our assembly instructions into a binary representation.

RTL for the SRC pipeline registers

Review: The whole processor

Introduction to Computer Organization and Architecture

The Processor: Datapath & Control.

Presentation transcript:

Instructor: Yuzhuang Hu

Final Exam! The final exam is scheduled on 7 th, August, Friday 7:00 pm – 10:00 pm

The Reduced Instruction Set Computer (RISC) The goal of a RISC architecture is high throughput and fast execution. To achieve these goals, accesses to memory are to be avoided. A RISC architecture has the following properties:  Memory accesses are restricted to load and store instructions, and data-manipulation instructions are register-to-register.  Addressing modes are limited in number.  Instruction formats are all of the same length.  Instructions perform elementary operations.

Datapath Organization The new datapath has bit registers. The address inputs are therefore five bits. The replacement of the single-bit position shifter with a barrel shifter to permit multiple-position (SH) shifting. In the function unit, the ALU is expanded to 32 bits. The constant unit performs zero fill for CS=0 and sign extension for CS=1. MUX A is added to provide a path from the updated PC, PC -1, for implementation of the JML instruction.

Datapath Organization contd. Adding an additional input to MUX D to implement the Set if Less Than (SLT) instruction. It is 1 when N is 1 and V is 0, or N is 0 and V is 1. A final difference is that the register file is no longer edge triggered and is no longer a part of a pipeline platform at the end of the write-back (WB) stage. In the second half of the cycle, it is possible to read data written into the register file during the first half of the same clock cycle. It is called a read-after-write register file.

Control Organization SH is added to IR, CS is added to the instruction decoder, MD is expanded to two bits. MUX C selects from three different sources for the next value of PC. BrA is formed from the sum of the updated PC value for the branch instruction and the target offset. BAA is used for the register jump. BS, PS and Z are used to select the next PC value.

Definition of Control Fields BS and FS

Data Hazards Unfortunately, there are other problems with pipeline operation that reduce throughput. Data Hazards Control Hazards

Data hazards Consider the following instructions 1.MOV R1, R5 2.ADD R2, R1, R6 3.ADD R3, R1, R2 IFDOFEXWB IFDOFEXWB IFDOFEXWB Mov R1, R5 Add R2, R1, R6 Add R3, R1, R2

A Program Based Solution Add NOPs to the program. IFDOFEXWB IFDOFEXWB IFDOFEXWB IFDOFEXWB IFDOFEXWB Mov R1, R5 Add R2, R1, R6 Add R3, R1, R2 NOP

Data Hazard Stall Insert bubbles to the pipeline. IFDOFEXWB IFDOF IFDOFEXWB IFDOF IFDOFEXWB Mov R1, R5 Add R2, R1, R6 Add R3, R1, R2 (Add R2, R1, R6) (Add R3, R1, R2) Data hazards detected, pipeline stalled, bubble launched

Data Forwarding No extra delay. IFDOFEXWB IFDOFEXWB IFDOFEXWB Mov R1, R5 Add R2, R1, R6 Add R3, R1, R2

Control Hazards 1 BZ R1, 18 2 MOV R2, R3 3 MOV R1, R2 4 MOV R4, R2 20 MOV R5, R6 IFDOFEXWB IFDOFEXWB IFDOFEXWB BZ R1, 18 MOV R2, R3 MOV R1, R2 IFDOFEXWB MOV R5, R6 Change in R2 Change in R1 PC set to 20

A Program Based Solution 1 BZ R1, 18 2 MOV R2, R3 3 MOV R1, R2 4 MOV R4, R2 20 MOV R5, R6 IFDOFEXWB IFDOFEXWB IFDOFEXWB BZ R1, 18 NOP IFDOFEXWB MOV R5, R6 No change PC set to 20

Branch Prediction 1 BZ R1, 18 2 MOV R2, R3 3 MOV R1, R2 4 MOV R4, R2 20 MOV R5, R6 IFDOFEXWB IFDOF IF BZ R1, 18 NOP IFDOFEXWB MOV R5, R6 No change PC set to 20 Branch detected and bubbles launched

CISC Architecture The goal of the CISC architecture is to match more closely the operations used in programming language and to provide instructions that facilitate compact programs and conserve memory. A purely CISC architecture has the following properties: Memory access is directly available to most types of instructions. Addressing modes are substantial in number. Instruction formats are of different lengths. Instructions perform both elementary and complex operations.

THANKS!