Latch versus Register Latch Register stores data when clock is low stores data when clock rises D Q D Q Clk Clk Clk Clk D D Q Q

Latches

Latch-Based Design N latch is transparent when f = 0 P latch is transparent when f = 1 f N P Logic Latch Latch Logic

Timing Definitions CLK t Register t t D Q D DATA CLK STABLE t t Q DATA su hold D DATA CLK STABLE t t c 2 q Q DATA STABLE t

Positive Feedback: Bi-Stability 1 A C B o 2 = o1 Vi2 1 o 1 o V V 5 2 i V 1 o V 5 i 2 V

Meta-Stability Gain should be larger than 1 in the transition region

Writing into a Static Latch Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states D CLK Forcing the state (can implement as NMOS-only) Converting into a MUX

Cascade connection of pass transistors V V V V V Vo R R R R C C C C = RC • n(n+1)/2, n: number of stages(transistors)  1/2 • n2 • RC Vo can reach up to V-VTN Vo(high) = V-3VTN Output of pass transistor better not be used as control variable for another gate. V V V Vo V

Cases where pass tr. is appropriate Multiplexer S A S B S

4-input Multiplexer using CMOS switch concept Removing contacting & interconnecting wire segments saves space.

Rules for transmission gate logic construction 1 A conducting path must not exist between two different inputs which could take different logic levels. If there is an overlap between 1 and 2, the intermediate node “y” will take an undefined potential, located between the 1 and 0. This potential will give rise to an erratic behavior of the logic, although it may not be detected by a switch-level simulator This problem can be solved by designing control signal with a mutual exclusion feature 1 X1 2 Y X1

Rules for transmission gate logic construction 2 When a branch has several transmission-gates in series, internal nodes can behave as a dynamic memory Such a gate cannot be considered as a pure static combinational logic gate, because the memory effect can give rise to false outputs, according to the history of successive inputs and control levels, Moreover, the output could be at high impedance if no buffer has been provided. This behavior dramatically increases the simulation and test problems

Rules for transmission gate logic construction 3 To avoid undesired high impedance states, care should be taken to always provide at least one conducting path between an input and the output The input variable sources must be low-impedance sources for the same reason a a Ex) 1-to-2 decoder 1 a X1 X1 1 a X2 X2 wrong good

Mux-Based Latches Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) CLK 1 D Q 1 D Q CLK

Mux-Based Latch

Mux-Based Latch NMOS only Non-overlapping clocks

Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

Master-Slave Register Multiplexer-based latch pair

Combinational logic circuit Flip-flops Combinational logic circuit

Basic Latch Both circuit are the same The only feedback path is the red line

Basic Latch Consider Set = 0, Reset =0

Basic Latch Consider S = 1, R =0 As S=1, NOR1 output must be 0 As NOR1 ouput = 0 and R =0, NOR2 output must be 1

Basic Latch Consider S = 0, R =1 As R = 1, NOR2 output must be 0

Basic Latch Consider R = 1 and S =1 As R = 1, NOR2 output must be 0 As S = 1, NOR1 output must be 0

Level sensitive and edge sensitive For a latch and flip-flop (FF), it can be level sensitive or edge sensitive Level sensitive means the latch / FF will copy input D to output Q when Clk = 1 Edge sensitive means that the latch / FF will only copy input D to output Q when Clk change from 0 -> 1 (positive edge trigger) / 1 -> 0 (negative edge trigger)

Level sensitive

Edge sensitive