Electrodeposited Photoresists for Wafer Applications

Nature of ED Resists ED stands for electrodeposited ED paint used by Ford since 1960 Emulsion of photoresist “Micelles” in water - 50 – 150 microns - Micelles contain the resist components - Micelles have a + or - charge Photoresist Micelle Polymer Photo Active Compound Solvents Dye

Deposits on all conductive surfaces Conformation on 3-D Structures Deposits on all conductive surfaces Intervia 3D-P over thick plated copper Forms a nearly conformal coating over 3-dimensional structures Allows the manufacture of features that are otherwise difficult or impossible to construct using conventional liquid resist technology Due to flowing, some thinning can be seen over sharp edges, especially with Eagle prior to exposure and cross-linking Because of the topography in these types of structures, exposure can best be accomplished with a shadow mask projection system or a laser direct writing system

Dow Electronic Materials ED Resists Intervia 3D-N Negative tone image / cathodic wafer (wafer has negative charge) Intervia 3D-P Positive-tone image / anodic wafer (wafer has positive charge)

Intervia 3D-N Coating Process Micelles migrate to cathodic substrate H2 O2 NR3+ - NR3+ H2O RCO2- Inert Anode Conductive Wafer (Cathode) RCO2- NR3+ RCO2- RCO2- NR3+ NR3+ NR3+ RCO2- NR3+ NR3+ RCO2- NR3+ NR3+

Self Limiting Behavior resist Because the deposited layer of photoresist is insulating, Thin areas are able to coat faster. -> healing of thin areas -> Conformal coatings -> uniform films

Deposition Current Profile Self Limiting Behavior Near Zero Current Deposition Current vs. Time Time Deposition Current

Intervia 3D-P Application Process Resist Coating - Coating Cycle . 100 - 300 V DC . 10 ASF peak . Potential applied for 10 - 20 seconds - Thickness Control . Temperature . Solvent Exposure 365 - 405 nm

Thickness vs. Temperature Thickness (microns) Weaker but significant inverse relationship between thickness and temperature - important to regulate thickness - Thickness controller effect far more dominant out ways Temperature (ºC)

Deposit Uniformity Thickness Uniformity Thickness (microns) Position As expect with self limiting process No edge bead Slight sensitivity to process parameters and hardware. Position

ED Resist Comparison Intervia 3D-N Negative working 6 – 100 µm final thickness 200-300 mJ/cm2 @365nm Organic acid develop / strip Acid and alkaline etches Resistant to many plating chemistries

ED Resist Comparison Intervia 3D-N Intervia 3D-P Negative working 6 - 100 µm final thickness 200-300 mJ/cm2 @365nm Organic acid develop / strip Acid and alkaline etches Resistant to many plating chemistries Intervia 3D-P Positive working 6 µm target final thickness 250-400 mJ/cm2 @405nm -CO3,-OH or TMAH develop Plating and acid etching Hydroxide or organic solvents

Tools ED Resist Coater for R&D and Low Volume Production Semitool ED Cell ED Resist Coater for R&D and Low Volume Production

Problems with Spin-on Resists 100µm feature spin coated with 6.0 µm of photoresist. Little or no coverage on outside corners Very thick coverage in inside corners and at bottom of the feature Image of 25µm lines patterned over the top of 45µm wide features

Coated Wafer Structures Source: Semitool SEM image of 6µm of electrophoretic photoresist deposited over a series of 92µm tall features. SEM image showing 5µm of electrophoretic photoresist deposited over a 300µm deep trench.

Examples of Wafer Processes Using Intervia ED Resists

Basic 3-D Test Structures source: Meco Sketch of proposed technology for wafer-through hole interconnects Set of 10, 20, 30 & 40 µm wide test slits reproduced at 150µm deep cavity SEM Source: Meco

Ni Plated Structures on Polyimide SEM photomicrographics of conformally electroplated Ni lines across polyimide grooves using Intervia 3D-P electrodeposition Source: Dow Electronic Materials

ShellCase Process ShellOP for Image Sensors and Light Detection Devices Dow ED Products Negative ED photoresist Developer Remover

Etching Conductive Vias with ED Resists a) Photolithography on thick resist b) Through-wafer etching (HDLP RIE) c) Thermal oxidation and polysilicon deposition (LPCVD) d) CVD metallization (W or Cu) and electro-plating (Cu only) e) Electrodeposited resist deposition f) Resist patterning by photo lithography g) Metal and polysilicon etching h) Photoresist removal a) e) b) f) c) g) d) h) Source: Quate Group, Stanford University

Source: Lindedre, Baltes, Gnaednger Backside Contacts SEM micrograph of final through-wafer vias Source: Lindedre, Baltes, Gnaednger

Backside Contacts through-hole sidewall SEM micrograph showing metallization on {111} sidewalls for elimination of uncontrolled light reflections. Source: Lindedre, Baltes, Gnaednger

Philips Thru Via Imaging

Philips Thru Via Imaging Quadruple leads in a single through-wafer hole and a toroid structure

Exposure Using Phase Gratings Source: Philips UV light photomask side view substrate phase grating cross section top view Schematic view of 3-D exposure using phase gratings

Plated Coils

Infineon ELASTec® Wafer Level Bumping Intervia 3D-P Resist Finished Bump

ELASTec® Process Steps 1 • Bump Print & Cure • Seedlayer Sputter (Ti/Cu) 2 • Reroute Plating (Cu, Ni, Au) 3 • Resist Strip • Seedlayer Etch

Elastic®

Silicon Optical Bench 2. Vias 2-D Diagram of SiOB-I. Number 1, 2 & 3 indicate the regions where cross sections are taken for the fabrication diagrams. Design II Interconnect: Partially shielded microstrip. (All dimensions are in microns) Source: Banerjee, Drayton

Impact of Resist Tone on Printed Defects

Intervia 3D-N Typical Application Process

Intervia 3D-N Application Process Chemical Clean Preposit Cleaner 742 Sulfuric acid based soak cleaner Removes fingerprints & soils 50 - 55 degrees C 2 - 3 minutes

Intervia 3D-N Application Process Chemical Clean Preposit Etch 748 Monopersulfate etchant Micro roughens copper (0.5 - 1.0 µm) 30°C 2 - 3 minutes

Intervia 3D-N Application Process Resist Coating Resist is sparged upon entry to fully wet the part Vibration of parts may be used in some applications to release air bubbles Part to be coated is the cathode Stainless steel anodes

Intervia 3D-N Coating Cycle Conductive Wafer (Cathode) Inert Anode NR3+ - NR3+ H2O H2 O2 RCO2-

Intervia 3D-N Coating Cell Vibrator Spargers SS Anode Part to be Coated

Intervia 3D-N Application Process Resist Coating Coating Cycle 100 - 300 V DC 10 ASF peak Potential applied for 10 - 20 seconds Thickness Control Temperature Coating Time Voltage

Typical Tmin Curve for Intervia 3D-N

Intervia 3D-N Application Process Conservation Rinse Reclaims resist drag-out Conservation resist is ultrafiltered to reclaim solids D.I. Final Rinse

Intervia 3D-N Topcoat Contains cellulose-based material in water Reduces tack of coating Reduces edge recession Dissolves quickly during development step

Intervia 3D-N Application Process Air knives Remove bulk moisture Promotes uniform drying Convection Dry 105°C 10 minutes

Intervia 3D-N Application Process Exposure 300 mJ/cm2 required at 5 micron resist thickness 365 nm peak Intensity affects required dose Subject to Low Intensity Reciprocity Law Failure (LIRLF) 10 mW/cm2 minimum recommended

Intervia 3D-N Application Process Development Intervia 3D-N Developer 38 - 42°C Clear time 30 - 120 seconds 50% breakpoint

Intervia 3D-N Application Process Plating Cupronal BP (copper) Auronal BP (gold) Solderon BP ( tin lead, lead free, low alpha lead) Nikal BP (nickel) Etching Cupric Chloride Ferric Chloride

Intervia 3D-N Application Process Stripping Intervia 3D-N Remover 50 - 65°C

Microfabrication Capabilities Etched features with 0.2 um tolerances Deep (through-wafer) etching Contoured plated features (photoresists and metals) Submicron multilayer feature-to-feature alignment Submicron die bonding Conformal AR coatings

…and thank you for your time and attention. MicroChem would like to thank Dow Electronic Materials for providing these materials… …and thank you for your time and attention.