Front-end Digitization for fast Imagers. Pradeep Kalavakuru, Inge Diehl Matter and Technologies Detector Development Motivation Benefits Intelligent Processing CMOS Scaling Challenge Solutions High Bandwidth Single-Photon Counting DSSC 4096 x 8 bit x 4.5 MHz ≈ 150 Gbps / chip → in-Pixel Memory (burst) Particle Tracking dSiPM 4096 x 1 bit x 3 MHz ≈ 12 Gbps / chip → fast Link (continuous) sensitive → short Connection large Margins in Time & Amplitude → robust early Digitization A D DEPFET Sensor with Signal Compression (DSSC) Digital Silicon Photomultiplier (dSiPM) Single-slope ADC Digital Front-end 15 mm TDC 236 µm Clock Trigger 32 element delay line Vcontrol DLL Ripple Counter 5 bit 7 bit Latch Encoder Phase Frequency Detector & Current Pump D C Q _ Hold Time Hit Counter 2 bit Anode Quench Recharge Serializer AQRC Vqt Vrt Trigger 3.3 V 1.2 V MEMORY 105 µm 64 x 64 Receivers 204 µm 14 mm FE + Control-Logic Offset Trimming 120 µm Comparator Gain Trimming 1.9 mm 2.1 mm 50 µm 57 µm 160 µm 55 µm V / I Reference 64 x Tx & GCC In Pixel Ping-Pong Buffering Ramp Generation with Gain Trimming (6 bit) Delay for Offset Trimming (4 bit) Differential Latches for Time Stamps Features Sampling Rate: 4.5 MHz …10 MHz Dynamic Range: 1 V Process: GF 130 nm CMOS, C4 Bumps Resolution: 8 bit Time stamp: 720 ps …300 ps Noise: 180 µVrms Temp. Stability: ±1% of Gain from -40°C … 40°C Supply: 1.1 V…1.4 V Power Peak: 818 µW Mean: 5 µW (Power Cycling) Global 8-bit Gray-Code Counter Time Stamps distributed over coplanar Wave Guides 16 x 16 In Pixel Active Quenching & Recharging Wired-OR Trigger Hit Counting Adjustable Recharge Start/Hold-Time (Pile-up Rejection) Global Delay-Lock Loop (fine TDC) Ripple Counter (coarse TDC) 32-to-5 bit Encoder Hit-Validation Thresholds (4 per Row, 2 per Matrix) Serial Links Gain → 320 LSB / V Features Process: GF 130 nm CMOS, SAC Bumps Frame Rate: 3 MHz Throughput: 1 Gbps … 1.6 Gbps Trigger Delay: <2 ns TDC Resolution: 12 bit TDC-Bin Width: 77 ps Supplies: 1.2 V, 3.3 V Power Dissipation: 140 mW (total) → 550 µW/Pixel 110 mW (IO) 30 mW (core) Anode Quench Recharge Quenching Time 6 - 260 ns Recharging Time 5 - 160 ns Vth ≈ 1 V σ = 0.16 Results (Room Temperature) Lab-Test Condition Power Cycling (10 Hz @ 200 µs) Storage Depth (800 Frames @ 4.5 MHz) Lab-Test Condition Pixel Enabling Global Test Input Separate TDC 3-MHz Frame Rate Gain ( LSB / V) INL (ADU) DNL (ADU) Automated Gain Trimming Trimming Spread ± 2% σmean = 0.4 LSB No missing Bins σmean = 0.18 LSB Max. Delay: 1.92 ns Uncertainty: 100 ps Bin Width: 77.25 ps ± 11.13 ps DNL: σ = 0.15 LSB INL: σ = 0.33 LSB Petra III (P65 Beam Line) Beam focused onto 8-µm Cu Foil Center of Energy Cu-Kα / Kβ → 8.155 keV Frame Rate → 2.6 MHz (every 2nd Event) With dSiMPl Sensor from MPG-HLL cps Mean-Count Rate → 230 kcts/s/Pixel Counts Mean Noise → ~ 80 e- Noise (e-) Mean Sensitivity → 0.72 keV/Bin Mean Noise peak → 41.86 Mean Signal peak → 50.03 Sensitivity → 1 keV / Bin ENC → ~80 e- 8.17 40 50 60 70 80 ADU 103 101 102 104 105 10 Counts Vbd ≈ 35 V (Breakdown) Vbias = Vbd + Vov (Overvoltage) Threshold of Front-end Inverter ≈ 1 V Noisy Pixel can be disabled Future Aspects On-Chip Power Management 65-nm CMOS On-Chip intelligent Data Processing Fast Links