Fiber Optic Transciever Buffer FPGA Data Pipeline Counter 18-bit Threshold Table 20MHz 12-bit (each) 80MHz 12-bit 80MHz 30-bit 80MHz 30-bit (31-bit?) 240MHz 1-bit (each) 20MHz ADC Deserializer 30 bits 30 (31?) bits Add address and (partial) timestamp Zero suppression: Add validity bit or set data to “invalid” code 80MHz 30-bit (31-bit?) Fiber Optic Transciever Buffer 80MHz 32-bit Fiber Optic Up to 3.5Gbps 30 (31?) bits 30 (31?) bits If valid, add to buffer Additional pipeline stages (if necessary)

FPGA Data Pipeline Pipeline design for 1 FEC/FEM, assuming only complete readout mode is used Zero suppression occurs while SCAs are being read out Only time cost is the amount of time it takes to fill the pipeline (around 5ns per event) Designed for full readout of all ASICs simultaneously Could be made to work with other readout modes, but extra logic would be required