R. van Langevelde, A.J. Scholten Philips Research, The Netherlands MOS Model 11 R. van Langevelde, A.J. Scholten and D.B.M. Klaassen Philips Research, The Netherlands MOS-AK Group Meeting’02 XFAB, Erfurt October 21, 2002

Introduction: MOS Model 11 Goals for MOS Model 11 (MM11): suitable for digital, analog and RF suitable for modern/future CMOS processes physics based simulation time comparable to MM9 number of parameters comparable to MM9 simple parameter extraction

Introduction: MOS Model 11 Model developed for accurate distortion analysis in circuit design: surface-potential-based model accurate transition weak  strong inversion symmetrical distortion accurate description of third-order derivatives (i.e. 3I/V3)

Introduction: MOS Model 11 implemented physical effects: mobility reduction bias-dependent series resistance velocity saturation conductance effects (CLM, DIBL, etc.) gate leakage current gate-induced drain leakage gate depletion quantum-mechanical effects bias-dependent overlap capacitances

Introduction: availability of MM11 public domain source code in C (including solver) documentation of model and parameter extraction http://www.semiconductors.philips.com/Philips_Models circuit simulators Pstar (Philips in-house) Spectre (Cadence) Hspice (Avant!) ADS (Agilent) Eldo (Mentor Graphics) HSIM (NASSDA)

Introduction: structure of MOS Model 11 W, L Junction diodes modelled by JUNCAP-model Geometry Scaling T Temperature Scaling Model Equations

Model Parameters & Extraction Summary MOS Model 11: outline Introduction DC-Model AC-Model Noise Model Model Parameters & Extraction Summary

DC-Model: VT -based model 10 -3 interpolation needed between subthreshold and superthreshold (e.g. BSIM4 and MM9) 10 -4 10 -5 IDS (A) 10 -6 10 -7 VSB = 0 V VDS = 1 V 10 -8 10 -9 Smoothing function 10 -10 1 2 VGS (V)

DC-Model: surface-potential-based model s-based model: 10 -4 I = I + I DS drift diff single equation for whole operation range: 10 -5 I 10 -6 diff IDS (A) 10 -7 Idrift = f(VGB ,s0 ,sL) 10 -8 VSB = 0 V 10 -9 Idiff = g(VGB ,s0 ,sL) 10 -10 VDS = 1 V I drift 10 -11 1 2 IDS = Idrift + Idiff VGS (V)

DC-Model: surface potential ys V = VSB at Source V = VDB at Drain Quasi-Fermi Potential V: V VGB EC EF Ei EV Gate Oxide Substrate

s = s(VGB ,V )  iterative solution  time consuming DC-Model: surface potential approximation  iterative solution  time consuming  approximation used: s = s(VGB ,V ) (Solid-State Electron. 44, 2000)

DC-Model: surface-potential-based model Description of ideal long-channel MOSFET For real devices several physical effects have to be taken into account: mobility effects conductance effects new models Special attention to: distortion drain-source symmetry

DC-Model: distortion behavior IOUT 1 2 Amplitude 3 4 VIN Harmonic 2nd-order distortion: cancels out in balanced circuit 3rd-order distortion: limits dynamic range  accurate description of 3rd-order derivatives

DC-Model: gate-bias induced distortion Gate-bias induced distortion for NMOS, W/L=10/1m 1 2 3 4 V GS (V) 10 -11 -10 -9 -8 -7 -6 -5 Harmonic Amplitude (A) SB = 0 V DS = 0.1 V HD2 HD3 HD1 T Mobility Reduction and Series-Resistance Symbols Measurements Lines MOS Model 11

DC-Model: conductance modeling Drain-bias induced distortion for NMOS W/L=10/1m 1 2 3 4 V DS (V) 10 -8 -7 -6 -5 -4 -3 Harmonic Amplitude (A) V = 0 V Static Feedback SB and V = 2.5 V GS Self-Heating HD1 HD2 HD3 Velocity Channel Length Modulation Weak-Avalanche Saturation

RF-distortion determined by DC model DC-Model: RF-distortion modeling RF-distortion determined by DC model f=16 MHz f=1 GHz NMOS, W/L=160/0.35mm, VDS=3.3 V, PIN=-5dBm

VT vs. s-based models Distortion modeling Symmetry Outline: DC-Model VT vs. s-based models Distortion modeling Symmetry Gate leakage current

DC-Model : drain-source symmetry Symmetry w.r.t. source and drain at VDS= 0  MOS models developed for VDS  0  for VDS < 0, source & drain are interchanged In order to preserve symmetry: IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB ) ideal current equation velocity saturation DIBL/static feedback smoothing function (linear/saturation region) Care has to be taken with the implementation of:

DC-Model : drain-source symmetry IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB ) Not valid for threshold-voltage-based models MOS Model 9

DC-Model : drain-source symmetry IDS( VGS , VDS , VSB ) = -IDS( VGD , VSD , VDB ) MOS Model 9 MOS Model 11 Care has to be taken to preserve symmetry

VT vs. s-based models Distortion modeling Symmetry Outline: DC-Model VT vs. s-based models Distortion modeling Symmetry Gate leakage current

DC-Model: gate leakage current Source Drain bulk VGS potential

Simplified relation: DC-Model: gate leakage current NMOS, VDS=0V Source Drain bulk VGS { tox JG NMOS, VDS=0V where: Simplified relation:

electron charge density DC-Model: gate leakage model NMOS (in inversion): Gate current density: Gate EV Oxide EC Ei EF Substrate - electron charge density tunnelling probability parameters Approximation (at VDS=0 V):

S D IG IGD IGS DC-Model: gate current components NMOS, tox=2 nm, Area=6 m2 VGS>0 S D IG IGD IGS

S D IG IGOV IGD IGS DC-Model: gate current components VGS>0 S D IG NMOS, tox=2 nm, Area=6 m2 IGOV IGD IGS

S D IG IGD IGS IGOV DC-Model: gate current components NMOS, tox=2 nm, Area=6 m2 S D IG IGD IGS IGOV VGS<0

S D IG IGD IGS IGB IGOV DC-Model: gate current components NMOS, tox=2 nm, Area=6 m2 VGS<<0 S D IG IGD IGS IGB IGOV

S D IG IGD IGS IGB IGOV DC-Model: gate current components NMOS, tox=2 nm, Area=6 m2 VGS<<0 S D IG IGD IGS IGB IGOV

DC-Model: gate leakage model determined by intrinsic region determined by overlap region NMOS, tox=2 nm, Area=6 m2

Model Parameters & Extraction Summary MOS Model 11: outline Introduction DC-Model AC-Model Noise Model Model Parameters & Extraction Summary

AC-Model: intrinsic charges + n+ p Intrinsic Capacitances: where i, j =G, S, D or B

 gate depletion effect AC-Model: input capacitance CGG charge model includes:  gate depletion effect tox=3.6nm  quantum-mechanical effects tox=3.2nm tox=3.6nm  accumulation physical tox=3.2nm PMOS, VDS=0 V, W/L=80*612/2.5mm

AC-Model: symmetry and reciprocity of capacitances VDS=0V symmetry (CiD=CiS) reciprocity (Cij=Cji) CBD-CBS vs. VG CDS-CSD vs. VG

AC-Model: bias-dependent overlap capacitance Gate n+ n+ + + + + + + - - - - - - Source n+ p n+ Bulk Source/Drain Two-terminal MOS-capacitance: accumulation and depletion region included introducing two parameters: kov and VFBov

AC-Model: bias-dependent overlap capacitance PMOS , VDS=0 V , W/L=152*612/0.18mm Short-channel MOSFET, 0.18mm CMOS

Model Parameters & Extraction Summary MOS Model 11: outline Introduction DC-Model AC-Model Noise Model Model Parameters & Extraction Summary

Noise Model: noise types in MOS transistor 1/f noise thermal noise induced gate noise induced gate noise This presentation is outlined as follows: After the introduction, we will discuss the silicon, on which the RF model parameters for CMOS18 are based. Next, the available models will be shortly introduced. After treating some examples on the single-device level, a circuit simulation example taken from practice will be given.

NMOS PMOS Noise Model: 1/f-noise 10-8 1 2 3 4 Vgs [Volt] PMOS model NMOS 10-9 10-10 10-11 1 2 3 4 Vgs [Volt] unified 1/f noise model: BSIM4, MM9 & MM11 bias dependence verified geometrical scaling verified (Kwok K. Hung et al., IEEE TED-37 (3), p.654, 1990; ibid. (5), p.1323, 1990)

Noise Model: thermal noise where: (F.M. Klaassen & J. Prins , Philips Res. Repts. 22, p.504, 1967) New expression (MM11) Old expression (BSIM,MM9)

Noise Model: thermal noise (II) 50 Noise Figure (NMOS, W/L=160/0.35mm, VDS=3.3V) (A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999) no hot electron effect needed to describe noise behaviour

Noise Model: thermal noise (III) 50 noise figure (no noise parameters needed)  verified on 0.35mm, 0.25mm and 0.18mm CMOS (A.J. Scholten et al., IEDM Tech. Dig., pp.155-158, 1999)

Model Parameters & Extraction Summary MOS Model 11: outline Introduction DC-Model AC-Model Noise Model Model Parameters & Extraction Summary

Parameters: model structure WL Geometry Scaling Temperature Scaling Model Equations 37 geometry scaling parameters 13 temperature scaling parameters 39 miniset parameters

Parameters: extraction strategy measurements ko extract miniset for each dut 0.1 0.15 0.2 0.25 5 10 15 Miniset Scaling 1/LE (1/m) ko (V1/2) determine temperature scaling determine geometry scaling parameter set example: 0.12m CMOS

Parameters: measurements required measurements per device 1 ID - VGS - curve for various VSB in linear region 2 ID - VDS - and gDS - VDS - curves for various VGS 3 IG - VGS - and IB - VGS - curves for various VDS 4 CGG - VGS - curve at VSB=VDS=0V (optional)

Parameters: extraction outline Measurements Miniset extraction Temperature scaling Geometry scaling

Parameters: DC miniset effect parameters threshold kO , B subthreshold slope mO flat-band voltage VFB poly depletion kP mobility reduction  , sr , ph , mob series resistance  , R velocity saturation sat conductance  , DIBL , sf , Th impact ionization a1 , a2 , a3 gate current IGINV , BINV , IGACC , BACC , IGOV

Parameters: miniset extraction strategy 1st-order estimation (optional) flat-band voltage/poly depletion somewhat different strategy for long-channel and short-channel devices (sub)threshold parameters mobility/series-resistance velocity saturation/conductance gate current  start with long- channel device impact ionization

Parameters: miniset extraction of long-channel device Step 1: 1st-order estimation doping concentration in polysilicon gate tox NP } 1st-order parameter estimate } { W miniset parameters L

Parameters: miniset extraction of long-channel device Step 1: 1st-order estimation optimize ID and gm on absolute error: B, ko,  and sr threshold mobility ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 1: 1st-order estimation optimize ID and gm on absolute error: B, ko,  and sr threshold mobility ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 2: VFB/poly-depletion (optional) optimize CGG on relative error: VFB, B, ko and 1/kP poly-depletion optimization region measurement error due to gate current CGG (pF) NMOS W/L=100/10m VGS (V)

Parameters: miniset extraction of long-channel device Step 2: VFB/poly-depletion (optional) optimize CGG on relative error: VFB, B, ko and 1/kP poly-depletion CGG (pF) VGS (V) NMOS W/L=100/10m

Parameters: miniset extraction of long-channel device Step 3: subthreshold parameters optimize ID on relative error: B, ko and mo measurement 1 optimization region ID (A) NMOS W/L=10/10m VGS (V)

Parameters: miniset extraction of long-channel device Step 3: subthreshold parameters optimize ID on relative error: B, ko and mo measurement 1 ID (A) NMOS W/L=10/10m VGS (V)

Parameters: miniset extraction of long-channel device Step 4: mobility parameters optimize ID and gm on relative error: , sr, ph and mob mobility reduction optimization region ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 4: mobility parameters optimize ID and gm on relative error: , sr, ph and mob mobility reduction ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 5: velocity saturation/conductance optimize ID on absolute error: sat velocity saturation conductance optimize gDS on relative error: , sf and Th ID (A) gDS (A/V) NMOS W/L=10/10m VDS (V) VDS (V)

Parameters: miniset extraction of long-channel device Step 5: velocity saturation/conductance optimize ID on absolute error: sat velocity saturation conductance optimize gDS on relative error: , sf and Th ID (A) gDS (A/V) NMOS W/L=10/10m VDS (V) VDS (V)

Parameters: miniset extraction of long-channel device Step 6: gate current parameters optimize IG on absolute error: Binv and IGINV gate-to-channel current IG (A) IG (A) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 6: gate current parameters optimize IG on absolute error: Binv and IGINV optimize IG on relative error: IGACC and IGOV gate-bulk & overlap current gate-to-channel current IG (A) IG (A) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Step 6: gate current parameters optimize IG on relative error: IGACC and IGOV gate-bulk & overlap current optimize IG on absolute error: Binv and IGINV IG (A) IG (A) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Repeat steps 3 through 6, e.g. step 4: optimize ID and gm on relative error: , sr, ph and mob error due to gate current optimization region ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: miniset extraction of long-channel device Repeat steps 3 through 6, e.g. step 4: optimize ID and gm on relative error: , sr, ph and mob ID (A) gm (A/V) NMOS W/L=10/10m VGS (V) VGS (V)

Parameters: extraction outline Measurements Miniset extraction Temperature scaling Geometry scaling

Parameters: geometry scaling rules two types of geometry scaling rules can be used: binning scaling rules fast and easy, however not physical reproduces minisets use 170 parameters per bin physical scaling rules somewhat more elaborate, but physical gives insight in technology use 90 parameters per technology

Parameters: physical geometry-scaling rules physical scaling rules have different forms per miniset parameter, e.g.: geometry scaling parameters or: scaling parameters determined from miniset values

Parameters: geometry scaling of body factor ko W = 10m NMOS MM11 scaling rule miniset values

Parameters: geometry scaling of gain factor  MM11 scaling rule PMOS W = 10m conventional scaling rule conventional scaling:

Parameters: geometry scaling: ID-VGS-curves physical geometry scaling fits of linear region (PMOS) VGS (V) ID (A) ID (mA) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Parameters: geometry scaling: gm-VGS-curves physical geometry scaling fits of linear region (PMOS) VGS (V) gm (A/V) gm (mA/V) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Parameters: geometry scaling: subthreshold curves physical geometry scaling fits of subthreshold region (PMOS) VGS (V) ID (A) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Parameters: geometry scaling: ID-VDS-curves physical geometry scaling fits of output curves (PMOS) VDS (V) ID (mA) ID (A) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Parameters: geometry scaling: gDS-VDS-curves physical geometry scaling fits of output curves (PMOS) gDS (A/V) VDS (V) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Parameters: geometry scaling: IG-VGS-curves physical geometry scaling fits of gate current (PMOS) VGS (V) |IG| (A) W/L = 10/10m W/L = 10/0.8m W/L = 10/0.12m

Excellent description of RF distortion Summary MOS Model 11, fulfills demands for advanced compact MOS modelling: use of s-formulations results in accurate description of moderate inversion region improved description of several physical effects results in accurate and symmetrical description of currents, charges, noise and distortion fulfills Compact Model Council benchmark tests parameters determined from I-V and C-V measurements no increase in number of parameters no increase in simulation time Excellent description of RF distortion

Why is MM11 in the public domain? Surface-potential-based model Appendices Why is MM11 in the public domain? Surface-potential-based model Accuracy of s-approximation Linear/saturation region transition Drain/source partitioning of IG Poly-depletion effect Quantum-mechanical effects Temperature scaling Binning geometry-scaling rules Literature

Hence it makes sense to have MM11 available for the outside world: Appendix: Why is MM11 in the public domain? W Semiconductors is a manufacturer with over 85% of sales to external customers Hence it makes sense to have MM11 available for the outside world: customers can use it vendors of EDA & extraction tools implement model facilitates communication about processes and wafer model is open for discussion and improvements

Appendix: surface-potential-based model + n+ p IDS

ID-VGS at VDS=1 V Surface Potential Drain Current Appendix: surface-potential-based model (II) ID-VGS at VDS=1 V Surface Potential Drain Current

ID-VDS at VGB - VFB =2 V Surface Potential Drain Current Appendix: surface-potential-based model (III) ID-VDS at VGB - VFB =2 V VDS=0 V Surface Potential Drain Current

Appendix: accuracy of surface potential approximation absolute error in ys relative error in IDS  error in IDS due to Dys error is negligible

Appendix: linear/saturation transition Model incorporates linear/saturation region for long-channel case:  Short-channel devices: Approximation used: s = s(VGB,VDSx + VSB) where: (K. Joardar et al, IEEE TED-45, pp. 134-148, 1998)

Appendix: gate current partitioning NMOS, tox=2 nm, W/L=10/0.6mm S IGD IGS D IG

Appendix: poly-depletion effect VGB > VFB depletion layer formed in Gate resulting in effective Gate potential: body factor of poly-silicon: Gate Oxide Substrate

Appendix: poly-depletion effect influence of poly-depletion (VDS=50mV , VSB=0V) 15 1 A) 10 m (pF) ( 0.5 k =2 k =2 P P GG I D 5 C W/L= 10/10 m m W/L= 10/10 m m 0.6 1.2 1.8 0.6 1.2 1.8 V (V) V (V) GS GS drain current gate capacitance

Appendix: poly-depletion effect 0.18m CMOS W/L=80*612/2.5m NMOS PMOS using electrical tox=3.6nm physical tox=3.2nm

Appendix: quantum-mechanical effects energy quantization charge centroid results in tox D E E C E F E i E V Gate Oxide Substrate results in VT

Appendix: quantum-mechanical effects inversion-layer is formed at distance y from interface (F. Stern, CRC Crit. Rev. Solid State Sci., pp.499-514, 1974) effective oxide thickness:

Appendix: quantum-mechanical effects 0.18m CMOS W/L=80*612/2.5m NMOS PMOS using physical tox=3.2nm

Appendix: temperature scaling temperature scaling rules of the form: or temperature scaling parameters where TR is room temperature miniset parameters at room temperature are exactly reproduced

Appendix: temperature-scaling extraction extraction strategy: 1st-order estimation (sub)threshold parameters somewhat different strategy for long-channel and short-channel devices mobility/series-resistance velocity saturation impact ionization  start extraction for long-channel device (use default values of temperature parameters as 1st-order estimation)

Appendix: temperature scaling long-channel device Step 1: subthreshold parameters optimize ID on relative error: T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VGS (V) VGS (V)

Appendix: temperature scaling long-channel device Step 1: subthreshold parameters optimize ID on relative error: T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VGS (V) VGS (V)

Appendix: temperature scaling long-channel device Step 2: mobility parameters optimize ID on relative error: , sr and ph T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VGS (V) VGS (V)

Appendix: temperature scaling long-channel device Step 2: mobility parameters optimize ID on relative error: , sr and ph T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VGS (V) VGS (V)

Appendix: temperature scaling long-channel device Step 3: velocity saturation optimize ID on relative error: sat T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VDS (V) VDS (V)

Appendix: temperature scaling long-channel device Step 3: velocity saturation optimize ID on relative error: sat T=125ºC T=-40ºC ID (A) ID (A) NMOS W/L=10/10m VDS (V) VDS (V)

Appendix: binning geometry-scaling rules minisets 1 2 3 4 12 11 10 9 8 7 6 5 16 15 14 13 binning rules based on physical scaling no parameter jumps at bin borders minisets are exactly reproduced at corners binning parameter set is calculated from minisets no extra extraction or optimization needed

Appendix: literature “Effect of gate-field dependent mobility degradation on distortion analysis in MOSFET’s”, R. v. Langevelde and F.M. Klaassen, IEEE Trans. El. Dev., Vol.44, p.2044, 1997 “Accurate drain conductance modeling for distortion analysis in MOSFETs”, R. v. Langevelde and F.M. Klaassen, IEDM’97 Technical Digest, p.313, 1997 “A compact MOSFET model for distortion analysis in analog circuit design”, R. v. Langevelde, Ph.D. Thesis, University of Technology Eindhoven, 1998 “Accurate thermal noise model for deep sub-micron CMOS”, A.J. Scholten et al., IEDM’99 Technical Digest, p.155, 1999 “An explicit surface-potential-based MOSFET model for circuit simulation”, R. v. Langevelde and F.M. Klaassen, Solid-State Electron., Vol.44, p.409, 2000 CMC benchmark tests

Appendix: literature “RF-Distortion characterisation of sub-micron CMOS”, L.F. Tiemeijer et al., Proc. ESSDERC’00, p.464, 2000 “RF-Distortion in deep sub-micron CMOS technologies”, R. v. Langevelde et al., IEDM’00 Technical Digest, p.807, 2000 “BSIM4 and MOS Model 11 benchmarks for MOSFET capacitances”, A.J. Scholten et al., CMC meeting, March 2001, http://www.eigroup.org/cmc “MOS Model 11, Level 1100’’, R. v. Langevelde, Nat.Lab. Unclassified Report NL-UR 2001/813, April 2001, see website “Compact MOS modelling for RF circuit simulation”, A.J. Scholten et al., Proc. SISPAD’01, p.194, 2001 “Advanced compact MOS modelling”, R. v. Langevelde et al., Proc. ESSDERC’01, p.81, 2001

Appendix: literature “Compact modelling of pocket-implanted MOSFETs”, A.J. Scholten et al., Proc. ESSDERC’01, p.311, 2001 “Gate current: Modeling, DL extraction and impact on RF performance”, R. v. Langevelde et al., IEDM’01 Technical Digest, p.289, 2001 “Parameter extraction for surface-potential based compact MOS Model 11”, R. v. Langevelde, Agilent World-Wide IC-CAP Users’ Conference, Dec. 2001 “MOS Model 11, Level 1101’’, R. v. Langevelde et al., Nat.Lab. Unclassified Report NL-UR 2002/802, June 2002, see website