1. Lecture 3: CMOS Transistor Theory

2. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics  pMOS I-V Characteristics  Gate and Diffusion Capacitance

3. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Goal of this section  Present intuitive understanding of device operation  Introduction of basic device equations  Introduction of models for manual analysis  Introduction of models for SPICE simulation  Future trends

4. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Diodes  Diodes do not appear in CMOS digital design as separate devices.  However, they are present as junctions and parasitic elements in all devices.  We will use a simple 1D analysis.  We will not concern ourselves too much with the DC behavior too much. 3: CMOS Transistor Theory4

5. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Depletion Region

6. CMOS VLSI DesignCMOS VLSI Design 4th Ed. DC Characteristics 3: CMOS Transistor Theory6

7. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Diode Current

8. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Forward Bias Typically avoided in Digital ICs

9. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Reverse Bias The Dominant Operation Mode

10. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Models for Manual Analysis

11. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Junction Capacitance 3: CMOS Transistor Theory11

12. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Junction Capacitance

13. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Junction Capacitance  m is known as the grading coefficient.  Keep in mind that C j is a small signal parameter. For large signal switching, an equivalent capacitance has to be calculated as  C eq has been defined such that the same amount of charge is transferred as the nonlinear model 3: CMOS Transistor Theory13

14. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Junction Capacitance  As a numerical example, a diode is switched between 0 and -2.5 V. The diode has C j0 = 2 X 10 -3 F/m 2, A D = 0.5 (  m) 2,  0 = 0.64 V, m = 0.5.  K eq = 0.622, C eq = 1.24 fF/(  m) 2. 3: CMOS Transistor Theory14

15. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Diffusion Capacitance

16. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Diffusion Capacitance  Effective in forward bias 3: CMOS Transistor Theory16

17. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Diffusion Capacitance  From this lifetime analysis of excess charge,  Note that C d is also a small signal capacitance 3: CMOS Transistor Theory17

18. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Other Diode Parameters  Secondary Effects –Resistivity of regions outside junction –Breakdown voltage –Temperature dependence  T has a linear dependence I S doubles every 8˚C Overall, current doubles every 12˚C. 3: CMOS Transistor Theory18

19. CMOS VLSI DesignCMOS VLSI Design 4th Ed. SPICE Model  The following summarize diode behavior:  n is called the emission coefficient and concentrates the non-idealities listed above. 3: CMOS Transistor Theory19

20. CMOS VLSI DesignCMOS VLSI Design 4th Ed. SPICE Parameters

21. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory21 Introduction  So far, we have treated transistors as ideal switches  An ON transistor passes a finite amount of current –Depends on terminal voltages –Derive current-voltage (I-V) relationships  Transistor gate, source, drain all have capacitance –I = C (  V/  t) ->  t = (C/I)  V –Capacitance and current determine speed

22. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory22 MOS Capacitor GGate and body form MOS capacitor OOperating modes –A–Accumulation –D–Depletion –I–Inversion

23. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory23 Terminal Voltages  Mode of operation depends on V g, V d, V s –V gs = V g – V s –V gd = V g – V d –V ds = V d – V s = V gs - V gd  Source and drain are symmetric diffusion terminals –By convention, source is terminal at lower voltage –Hence V ds  0  nMOS body is grounded. First assume source voltage is 0 too.  Three regions of operation –Cutoff –Linear (Resistive) –Saturation (Active)

24. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory24 nMOS Cutoff  No channel  I ds ≈ 0

25. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory25 nMOS Linear  Channel forms  Current flows from d to s –e - from s to d  I ds increases with V ds  Similar to linear resistor

26. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory26 nMOS Saturation  Channel pinches off  I ds independent of V ds  We say current saturates  Similar to current source

27. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory27 I-V Characteristics  In Linear region, I ds depends on –How much charge is in the channel? –How fast is the charge moving?

28. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory28 Channel Charge  MOS structure looks like parallel plate capacitor while operating in inversions –Gate – oxide – channel  Q channel = CV  C = C g =  ox WL/t ox = C ox WL  V = V gc – V t = (V gs – V ds /2) – V t C ox =  ox / t ox

29. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory29 Carrier velocity  Charge is carried by e-  Electrons are propelled by the lateral electric field between source and drain –E = V ds /L  Carrier velocity v proportional to lateral E-field –v =  E  called mobility  Time for carrier to cross channel: –t = L / v

30. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory30 nMOS Linear I-V  Now we know –How much charge Q channel is in the channel –How much time t each carrier takes to cross

31. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory31 nMOS Saturation I-V  If V gd < V t, channel pinches off near drain –When V ds > V dsat = V gs – V t  Now drain voltage no longer increases current

32. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory32 nMOS I-V Summary  Shockley 1 st order transistor models

33. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory33 Example  Your book will be using a 0.6  m process –From AMI Semiconductor –t ox = 100 Å –  = 350 cm 2 /V*s –V t = 0.7 V  Plot I ds vs. V ds –V gs = 0, 1, 2, 3, 4, 5 –Use W/L = 4/2

34. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory34 pMOS I-V  All dopings and voltages are inverted for pMOS –Source is the more positive terminal  Mobility  p is determined by holes –Typically 2-3x lower than that of electrons  n –120 cm 2 /Vs in AMI 0.6  m process  Thus pMOS must be wider to provide same current –In this class, assume  n /  p = 2

35. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory35 Capacitance  Any two conductors separated by an insulator have capacitance  Gate to channel capacitor is very important –Creates channel charge necessary for operation  Source and drain have capacitance to body –Across reverse-biased diodes –Called diffusion capacitance because it is associated with source/drain diffusion

36. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Level 1 Implementation in SPICE  Including the channel length modulation, body effect and overlaps, 3: CMOS Transistor Theory36

37. CMOS VLSI DesignCMOS VLSI Design 4th Ed. The Body Effect

38. CMOS VLSI DesignCMOS VLSI Design 4th Ed. SPICE Model NameSymbolSPICE Name Type Lateral DiffusionLDLD LDPhysical Oxide Thicknesst ox TOXPhysical Channel length modulation LAMBDAPhysical Surface Mobility  U0Physical Substrate DopingNANA NSUBPhysical Current Parameterkpkp KPElectrical Work Function SS PHIElectrical Threshold VoltageV T0 VTOElectrical Body Effect Parameter  GAMMAElectrical 3: CMOS Transistor Theory38

39. CMOS VLSI DesignCMOS VLSI Design 4th Ed. SPICE Model  Electrical parameters override when provided.  Otherwise, they are calculated from physical parameters.  LAMBDA is an empirical parameter. 3: CMOS Transistor Theory39

40. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Level 2 Implementation in SPICE  Now, let us remove some of the wrong assumptions.  Voltage across channel is not constant any more  The threshold voltage is not a constant any more 3: CMOS Transistor Theory40

41. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Level 2 Implementation in SPICE  To find the equation in the active region, take the derivative of I D and equate to 0.  V DS = V DS,sat when I D is maximum.  Note that I D is dependent on  even if V SB = 0.  V T is not explicitly used in the equations. 3: CMOS Transistor Theory41

42. CMOS VLSI DesignCMOS VLSI Design 4th Ed. More Corrections  Mobility is reduced with increasing gate voltage. –We will study this effect in detail later.  Current conduction occurs below the threshold voltage. –We will study this effect later.  Channel length modulation has to be corrected.  Threshold voltage depends on W and L.  Parasitic resistances in the source and drain  Latchup  Speed limit of carriers 3: CMOS Transistor Theory42

43. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Speed Limit of Carriers  Ohm’s Law is not true 3: CMOS Transistor Theory43

44. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Speed Limit of Carriers  Velocity is proportional to electric field for low fields  Velocity is saturated for high fields  To ensure continuity, use the following approximation for velocity.  Then, 3: CMOS Transistor Theory44

45. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Speed Limit of Carriers  That equation is still too complex for hand analysis.  Substitute the values at the critical electric field to find the current at the transition point.  An even simpler approach is as follows 3: CMOS Transistor Theory45

46. CMOS VLSI DesignCMOS VLSI Design 4th Ed. A Unified Model for Manual Analysis

47. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Transistor Model for Manual Analysis

48. CMOS VLSI DesignCMOS VLSI Design 4th Ed. The Transistor as a Switch

49. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Drain-Source Resistance  Large signal drain-source resistance is a nonlinear quantity varying across operating regions.  One can define an equivalent resistance  For a weakly nonlinear function, 3: CMOS Transistor Theory49

50. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Drain-Source Resistance  Applying the general formula for a transistor switching from V DD to V DD /2,  Alternatively, using the endpoints and averaging, 3: CMOS Transistor Theory50

51. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Drain-Source Resistance

52. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Drain-Source Resistance

53. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Drain-Source Resistance  Note the following –R is inversely proportional to W/L –For V DD >> V T + V D,sat /2, R is independent of V DD. –When V DD is close to V T, resistance increases. 3: CMOS Transistor Theory53

54. CMOS VLSI DesignCMOS VLSI Design 4th Ed. MOS Capacitances 3: CMOS Transistor Theory54

55. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory55 Gate Capacitance  Approximate channel as connected to source  C gs =  ox WL/t ox = C ox WL = C permicron W  C permicron is typically about 2 fF/  m

56. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Gate Capacitance Operation RegionC gb C gs C gd Cut-offC ox WL eff C ov Resistive0C ox WL eff /2 + C ov Active0(2/3) C ox WL eff + C ov C ov 3: CMOS Transistor Theory56

57. CMOS VLSI DesignCMOS VLSI Design 4th Ed. 3: CMOS Transistor Theory57 Diffusion Capacitance  C sb, C db  Undesirable, called parasitic capacitance  Capacitance depends on area and perimeter –Use small diffusion nodes –Comparable to C g for contacted diff –½ C g for uncontacted –Varies with process

58. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Capacitances in 0.25  m CMOS Process

59. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Sub-Threshold Conduction 00.511.522.5 10 -12 10 -10 10 -8 10 -6 10 -4 10 -2 V GS (V) I D (A) VTVT Linear Exponential Quadratic Typical values for S: 60.. 100 mV/decade The Slope Factor S is  V GS for I D2 /I D1 =10

60. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Sub-Threshold I D vs V GS V DS from 0 to 0.5V

61. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Sub-Threshold I D vs V DS V GS from 0 to 0.3V

62. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Scaling ParameterRelationFull ScalingFixed V scaling General Scaling W, L, t ox -1/S V DD, V T -1/S11/U N SUB V/W 2 depl SS2S2 S 2 /U Area/DeviceWL1/S 2 C ox 1/t ox SSS C gate C ox WL1/S k n, k p C ox W/LSSS 3: CMOS Transistor Theory62

63. CMOS VLSI DesignCMOS VLSI Design 4th Ed. Scaling (Continued) ParameterRelationFull ScalingFixed V Scaling General Scaling I D,sat C ox WV1/S11/U Current Density I D,sat /AreaSS2S2 S 2 /U R on V/I D,sat 111 Intrinsic Delay R on C gate 1/S PowerI D,sat V1/S 2 11/U 2 Power Density Power/Area1S2S2 S 2 /U 2 3: CMOS Transistor Theory63