Design and Implementation of VLSI Systems (EN1600) Lecture11: Delay Estimation Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson] S. Reda EN160 SP’08

Circuit characterization: delay and power estimation Delay estimation Logical effort for delay estimation Power estimation Interconnects and wire engineering Scaling theory S. Reda EN160 SP’08

Delay definitions tpdr: rising propagation delay From input to rising output crossing VDD/2 tpdf: falling propagation delay From input to falling output crossing VDD/2 tpd: average propagation delay. tpd = (tpdr + tpdf)/2 tcdr: rising contamination (best-case) delay tcdf: falling contamination (best-case) delay tcd: average contamination delay. tpd = (tcdr + tcdf)/2 tr: rise time From output crossing 0.2 VDD to 0.8 VDD tf: fall time From output crossing 0.8 VDD to 0.2 VDD S. Reda EN160 SP’08

How to calculate delay? Just run SPICE! Time consuming Not very useful for designers in evaluating different options and optimizing different parameters We need a simple way to estimate delay for “what if” scenarios. Fidelity vs. accuracy S. Reda EN160 SP’08

Transistor resistance In the linear region Not accurate, but at least shows that the resistance is proportional to L/W and decreases with Vgs If R/C are for a unit size transistor then a transistor of K unit width has KC capacitance and R/K resistance The resistance of a PMOS transistor = 2× resistance of NMOS transistor of the same size S. Reda EN160 SP’08

Switch-level RC models Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width S. Reda EN160 SP’08

Inverter RC delay estimate Estimate the delay of a fanout-of-1 inverter in response to a step input function tpd = 6RC S. Reda EN160 SP’08

Elmore delay model ON transistors look like resistors Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder S. Reda EN160 SP’08

Example: 3-input NAND gate Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). S. Reda EN160 SP’08

Example: 3-input NAND gate Annotate the 3-input NAND gate with gate and diffusion capacitance S. Reda EN160 SP’08

Example: 3-input NAND gate Annotate the 3-input NAND gate with gate and diffusion capacitance S. Reda EN160 SP’08

Computing the rise and fall delays Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. S. Reda EN160 SP’08

Delay components Delay has two components: Parasitic delay (due to gate own diffusion capacitance) 6 or 7 RC Independent of load Effort delay 4h RC Proportional to load capacitance S. Reda EN160 SP’08

Contamination delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If both inputs fall simultaneously Order of inputs also impact propagation delay. Which is better AB=10 -> 11 or AB=01 ->11? S. Reda EN160 SP’08

Diffusion capacitance we assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too S. Reda EN160 SP’08

Layout Comparison Which layout is better? S. Reda EN160 SP’08