1. UNIT-II Stick Diagrams

2. Stick Diagrams
Stick Diagrams N+ N+

3. Stick Diagrams
Stick Diagrams
Gnd
VDD X
VDD
Gnd
Stick
Diagram

4. Stick Diagrams
Stick Diagrams
Gnd
VDD X
VDD
Gnd

5. Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon.
stick diagrams are a means of capturing topography and layer information using simple diagrams.
Stick diagrams convey layer information through colour codes (or monochrome encoding).
Acts as an interface between symbolic circuit and the actual layout.

6. Stick Diagrams Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.

7. Stick Diagrams Does not show Exact placement of components
Transistor sizes
Wire lengths, wire widths, tub boundaries.
Any other low level details such as parasitics..

8. Stick Diagrams – Notations
Metal 1
Can also draw
in shades of
gray/line style.
poly
ndiff
pdiff
Similarly for contacts, via, tub etc..

9. Stick Diagrams – Some rules
When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.

10. Stick Diagrams – Some rules
When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).

11. Stick Diagrams – Some rules
When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.

12. Stick Diagrams – Some rules
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.

13. How to draw Stick Diagrams

14. Stick Diagrams

15. Stick Diagrams
Power A
Out C B
Ground

16. Introduction to CMOS VLSI Design MOS devices: static and dynamic behavior

17. Outline DC Response Logic Levels and Noise Margins Transient Response
Delay Estimation

18. DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter
When Vin = 0 -> Vout = VDD
When Vin = VDD -> Vout = 0
In between, Vout depends on
transistor size and current
By KCL, must settle such that
Idsn = |Idsp|
We could solve equations
But graphical solution gives more insight

19. Transistor Operation Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in
Cutoff?
Linear?
Saturation?

20. nMOS Operation Cutoff Linear Saturated Vgsn < Vgsn > Vdsn <

21. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn

22. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vdsn > Vgsn – Vtn
Vgsn = Vin
Vdsn = Vout

23. nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Vgsn = Vin
Vdsn = Vout

24. pMOS Operation Cutoff Linear Saturated Vgsp > Vgsp < Vdsp >

25. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
MOS equations

26. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vdsp < Vgsp – Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
MOS equations

27. pMOS Operation Cutoff Linear Saturated Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0

28. I-V Characteristics
Make pMOS is wider than nMOS such that bn = bp

29. Current vs. Vout, Vin

30. Load Line Analysis For a given Vin: Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in

31. Load Line Analysis
Vin = 0
MOS equations

32. Load Line Analysis
Vin = 0.2VDD

33. Load Line Analysis
Vin = 0.4VDD
MOS equations

34. Load Line Analysis
Vin = 0.6VDD

35. Load Line Analysis
Vin = 0.8VDD

36. Load Line Analysis
Vin = VDD

37. Load Line Summary

38. DC Transfer Curve
Transcribe points onto Vin vs. Vout plot

39. Operating Regions Revisit transistor operating regions Region nMOS
pMOS A
Cutoff
Linear B
Saturation C D E

40. Beta Ratio If bp / bn  1, switching point will move from VDD/2
Called skewed gate
Other gates: collapse into equivalent inverter

41. Noise Margins
How much noise can a gate input see before it does not recognize the input?

42. Logic Levels
To maximize noise margins, select logic levels at

43. Logic Levels To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic

44. Transient Response DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes
Requires solving differential equations
Input is usually considered to be a step or ramp
From 0 to VDD or vice versa

45. Inverter Step Response
Ex: find step response of inverter driving load cap

46. Inverter Step Response
Ex: find step response of inverter driving load cap

47. Inverter Step Response
Ex: find step response of inverter driving load cap

48. Inverter Step Response
Ex: find step response of inverter driving load cap

49. Inverter Step Response
Ex: find step response of inverter driving load cap

50. Inverter Step Response
Ex: find step response of inverter driving load cap

51. Delay Definitions tpdr: rising propagation delay
From input to rising output crossing VDD/2
tpdf: falling propagation delay
From input to falling output crossing VDD/2
tpd: average propagation delay
tpd = (tpdr + tpdf)/2
tr: rise time
From output crossing 0.2 VDD to 0.8 VDD
tf: fall time
From output crossing 0.8 VDD to 0.2 VDD

52. Delay Definitions tcdr: rising contamination delay
From input to rising output crossing VDD/2
tcdf: falling contamination delay
From input to falling output crossing VDD/2
tcd: average contamination delay
tpd = (tcdr + tcdf)/2

53. Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations numerically
Uses more accurate I-V models too!
But simulations take time to write

54. Delay Estimation We would like to be able to easily estimate delay
Not as accurate as simulation
But easier to ask “What if?”
The step response usually looks like a 1st order RC response with a decaying exponential.
Use RC delay models to estimate delay
C = total capacitance on output node
Use effective resistance R
So that tpd = RC
Characterize transistors by finding their effective R
Depends on average current as gate switches

55. RC Delay Models Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width

56. Delay Components Delay has two parts Parasitic delay Effort delay
6 or 7 RC
Independent of load
Effort delay
4h RC
Proportional to load capacitance

57. Diffusion Capacitance
we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
Reduces output capacitance by 2C
Merged uncontacted diffusion might help too